1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @ifinfo |
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10 | @end ifinfo |
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11 | @chapter Port Specific Information |
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12 | |
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13 | This chaper provides a general description of the type of |
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14 | architecture specific information which is in each of |
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15 | the architecture specific chapters that follow. The outline |
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16 | of this chapter is identical to that of the architecture |
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17 | specific chapters. |
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18 | |
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19 | In each of the architecture specific chapters, this |
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20 | introductory section will provide an overview of the |
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21 | architecture |
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22 | |
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23 | @subheading Architecture Documents |
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24 | |
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25 | In each of the architecture specific chapters, this |
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26 | section will provide pointers on where to obtain |
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27 | documentation. |
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28 | |
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29 | @c |
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30 | @c |
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31 | @c |
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32 | @section CPU Model Dependent Features |
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33 | |
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34 | Microprocessors are generally classified into families with a variety of |
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35 | CPU models or implementations within that family. Within a processor |
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36 | family, there is a high level of binary compatibility. This family |
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37 | may be based on either an architectural specification or on maintaining |
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38 | compatibility with a popular processor. Recent microprocessor families |
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39 | such as the SPARC or PowerPC are based on an architectural specification |
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40 | which is independent or any particular CPU model or implementation. |
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41 | Older families such as the M68xxx and the iX86 evolved as the manufacturer |
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42 | strived to produce higher performance processor models which maintained |
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43 | binary compatibility with older models. |
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44 | |
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45 | RTEMS takes advantage of the similarity of the various models within a |
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46 | CPU family. Although the models do vary in significant ways, the high |
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47 | level of compatibility makes it possible to share the bulk of the CPU |
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48 | dependent executive code across the entire family. Each processor family |
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49 | supported by RTEMS has a list of features which vary between CPU models |
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50 | within a family. For example, the most common model dependent feature |
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51 | regardless of CPU family is the presence or absence of a floating point |
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52 | unit or coprocessor. When defining the list of features present on a |
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53 | particular CPU model, one simply notes that floating point hardware |
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54 | is or is not present and defines a single constant appropriately. |
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55 | Conditional compilation is utilized to include the appropriate source |
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56 | code for this CPU model's feature set. It is important to note that |
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57 | this means that RTEMS is thus compiled using the appropriate feature set |
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58 | and compilation flags optimal for this CPU model used. The alternative |
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59 | would be to generate a binary which would execute on all family members |
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60 | using only the features which were always present. |
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61 | |
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62 | The set of CPU model feature macros are defined in the file |
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63 | @code{cpukit/score/cpu/CPU/rtems/score/cpu.h} based upon the GNU tools |
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64 | multilib variant that is appropriate for the particular CPU model defined |
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65 | on the compilation command line. |
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66 | |
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67 | In each of the architecture specific chapters, this section presents |
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68 | the set of features which vary across various implementations of the |
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69 | architecture that may be of importance to RTEMS application developers. |
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70 | |
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71 | The subsections will vary amongst the target architecture chapters as |
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72 | the specific features may vary. However, each port will include a few |
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73 | common features such as the CPU Model Name and presence of a hardware |
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74 | Floating Point Unit. The common features are described here. |
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75 | |
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76 | @subsection CPU Model Name |
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77 | |
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78 | The macro @code{CPU_MODEL_NAME} is a string which designates |
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79 | the name of this CPU model. For example, for the MC68020 |
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80 | processor model from the m68k architecture, this macro |
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81 | is set to the string "mc68020". |
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82 | |
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83 | @subsection Floating Point Unit |
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84 | |
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85 | In most architectures, the presence of a floating point unit is an option. |
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86 | It does not matter whether the hardware floating point support is |
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87 | incorporated on-chip or is an external coprocessor as long as it |
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88 | appears an FPU per the ISA. However, if a hardware FPU is not present, |
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89 | it is possible that the floating point emulation library for this |
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90 | CPU is not reentrant and thus context switched by RTEMS. |
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91 | |
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92 | RTEMS provides two feature macros to indicate the FPU configuration: |
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93 | |
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94 | @itemize @bullet |
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95 | |
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96 | @item CPU_HARDWARE_FP |
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97 | is set to TRUE to indicate that a hardware FPU is present. |
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98 | |
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99 | @item CPU_SOFTWARE_FP |
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100 | is set to TRUE to indicate that a hardware FPU is not present and that |
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101 | the FP software emulation will be context switched. |
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102 | |
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103 | @end itemize |
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104 | |
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105 | @c |
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106 | @c |
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107 | @c |
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108 | @section Calling Conventions |
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109 | |
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110 | Each high-level language compiler generates subroutine entry and exit |
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111 | code based upon a set of rules known as the compiler's calling convention. |
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112 | These rules address the following issues: |
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113 | |
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114 | @itemize @bullet |
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115 | @item register preservation and usage |
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116 | @item parameter passing |
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117 | @item call and return mechanism |
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118 | @end itemize |
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119 | |
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120 | A compiler's calling convention is of importance when |
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121 | interfacing to subroutines written in another language either |
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122 | assembly or high-level. Even when the high-level language and |
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123 | target processor are the same, different compilers may use |
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124 | different calling conventions. As a result, calling conventions |
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125 | are both processor and compiler dependent. |
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126 | |
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127 | @subsection Calling Mechanism |
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128 | |
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129 | In each of the architecture specific chapters, this subsection will |
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130 | describe the instruction(s) used to perform a @i{normal} subroutine |
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131 | invocation. All RTEMS directives are invoked as @i{normal} C language |
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132 | functions so it is important to the user application to understand the |
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133 | call and return mechanism. |
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134 | |
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135 | @subsection Register Usage |
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136 | |
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137 | In each of the architecture specific chapters, this subsection will |
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138 | detail the set of registers which are @b{NOT} preserved across subroutine |
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139 | invocations. The registers which are not preserved are assumed to be |
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140 | available for use as scratch registers. Therefore, the contents of these |
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141 | registers should not be assumed upon return from any RTEMS directive. |
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142 | |
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143 | In some architectures, there may be a set of registers made available |
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144 | automatically as a side-effect of the subroutine invocation |
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145 | mechanism. |
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146 | |
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147 | @subsection Parameter Passing |
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148 | |
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149 | In each of the architecture specific chapters, this subsection will |
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150 | describe the mechanism by which the parameters or arguments are passed |
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151 | by the caller to a subroutine. In some architectures, all parameters |
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152 | are passed on the stack while in others some are passed in registers. |
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153 | |
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154 | @subsection User-Provided Routines |
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155 | |
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156 | All user-provided routines invoked by RTEMS, such as |
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157 | user extensions, device drivers, and MPCI routines, must also |
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158 | adhere to these calling conventions. |
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159 | |
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160 | @c |
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161 | @c |
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162 | @c |
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163 | @section Memory Model |
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164 | |
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165 | A processor may support any combination of memory |
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166 | models ranging from pure physical addressing to complex demand |
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167 | paged virtual memory systems. RTEMS supports a flat memory |
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168 | model which ranges contiguously over the processor's allowable |
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169 | address space. RTEMS does not support segmentation or virtual |
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170 | memory of any kind. The appropriate memory model for RTEMS |
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171 | provided by the targeted processor and related characteristics |
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172 | of that model are described in this chapter. |
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173 | |
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174 | @subsection Flat Memory Model |
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175 | |
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176 | Most RTEMS target processors can be initialized to support a flat address |
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177 | space. Although the size of addresses varies between architectures, on |
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178 | most RTEMS targets, an address is 32-bits wide which defines addresses |
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179 | ranging from 0x00000000 to 0xFFFFFFFF (4 gigabytes). Each address is |
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180 | represented by a 32-bit value and is byte addressable. The address may be |
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181 | used to reference a single byte, word (2-bytes), or long word (4 bytes). |
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182 | Memory accesses within this address space may be performed in little or |
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183 | big endian fashion. |
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184 | |
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185 | On smaller CPU architectures supported by RTEMS, the address space |
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186 | may only be 20 or 24 bits wide. |
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187 | |
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188 | If the CPU model has support for virtual memory or segmentation, it is |
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189 | the responsibility of the Board Support Package (BSP) to initialize the |
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190 | MMU hardware to perform address translations which correspond to flat |
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191 | memory model. |
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192 | |
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193 | In each of the architecture specific chapters, this subsection will |
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194 | describe any architecture characteristics that differ from this general |
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195 | description. |
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196 | |
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197 | @c |
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198 | @c |
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199 | @c |
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200 | @section Interrupt Processing |
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201 | |
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202 | Different types of processors respond to the occurrence of an interrupt |
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203 | in its own unique fashion. In addition, each processor type provides |
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204 | a control mechanism to allow for the proper handling of an interrupt. |
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205 | The processor dependent response to the interrupt modifies the current |
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206 | execution state and results in a change in the execution stream. Most |
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207 | processors require that an interrupt handler utilize some special control |
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208 | mechanisms to return to the normal processing stream. Although RTEMS |
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209 | hides many of the processor dependent details of interrupt processing, |
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210 | it is important to understand how the RTEMS interrupt manager is mapped |
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211 | onto the processor's unique architecture. |
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212 | |
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213 | RTEMS supports a dedicated interrupt stack for all architectures. |
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214 | On architectures with hardware support for a dedicated interrupt stack, |
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215 | it will be initialized such that when an interrupt occurs, the processor |
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216 | automatically switches to this dedicated stack. On architectures without |
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217 | hardware support for a dedicated interrupt stack which is separate from |
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218 | those of the tasks, RTEMS will support switching to a dedicated stack |
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219 | for interrupt processing. |
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220 | |
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221 | Without a dedicated interrupt stack, every task in |
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222 | the system MUST have enough stack space to accommodate the worst |
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223 | case stack usage of that particular task and the interrupt |
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224 | service routines COMBINED. By supporting a dedicated interrupt |
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225 | stack, RTEMS significantly lowers the stack requirements for |
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226 | each task. |
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227 | |
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228 | A nested interrupt is processed similarly with the exception that since |
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229 | the CPU is already executing on the interrupt stack, there is no need |
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230 | to switch to the interrupt stack. |
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231 | |
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232 | In some configurations, RTEMS allocates the interrupt stack from the |
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233 | Workspace Area. The amount of memory allocated for the interrupt stack |
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234 | is user configured and based upon the @code{confdefs.h} parameter |
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235 | @code{CONFIGURE_INTERRUPT_STACK_SIZE}. This parameter is described |
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236 | in detail in the Configuring a System chapter of the User's Guide. |
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237 | On configurations in which RTEMS allocates the interrupt stack, during |
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238 | the initialization process, RTEMS will also install its interrupt stack. |
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239 | In other configurations, the interrupt stack is allocated and installed |
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240 | by the Board Support Package (BSP). |
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241 | |
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242 | In each of the architecture specific chapters, this section discesses |
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243 | the interrupt response and control mechanisms of the architecture as |
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244 | they pertain to RTEMS. |
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245 | |
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246 | @subsection Vectoring of an Interrupt Handler |
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247 | |
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248 | In each of the architecture specific chapters, this subsection will |
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249 | describe the architecture specific details of the interrupt vectoring |
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250 | process. In particular, it should include a description of the |
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251 | Interrupt Stack Frame (ISF). |
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252 | |
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253 | @subsection Interrupt Levels |
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254 | |
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255 | In each of the architecture specific chapters, this subsection will |
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256 | describe how the interrupt levels available on this particular architecture |
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257 | are mapped onto the 255 reserved in the task mode. The interrupt level |
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258 | value of zero (0) should always mean that interrupts are enabled. |
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259 | |
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260 | Any use of an interrupt level that is is not undefined on a particular |
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261 | architecture may result in behavior that is unpredictable. |
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262 | |
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263 | @subsection Disabling of Interrupts by RTEMS |
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264 | |
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265 | During the execution of directive calls, critical sections of code may |
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266 | be executed. When these sections are encountered, RTEMS disables all |
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267 | external interrupts before the execution of this section and restores |
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268 | them to the previous level upon completion of the section. RTEMS has |
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269 | been optimized to ensure that interrupts are disabled for the shortest |
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270 | number of instructions possible. Since the precise number of instructions |
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271 | and their execution time varies based upon target CPU family, CPU model, |
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272 | board memory speed, compiler version, and optimization level, it is |
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273 | not practical to provide the precise number for all possible RTEMS |
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274 | configurations. |
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275 | |
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276 | Historically, the measurements were made by hand analyzing and counting |
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277 | the execution time of instruction sequences during interrupt disable |
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278 | critical sections. For reference purposes, on a 16 Mhz Motorola |
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279 | MC68020, the maximum interrupt disable period was typically approximately |
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280 | ten (10) to thirteen (13) microseconds. This architecture was memory bound |
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281 | and had a slow bit scan instruction. In contrast, during the same |
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282 | period a 14 Mhz SPARC would have a worst case disable time of approximately |
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283 | two (2) to three (3) microseconds because it had a single cycle bit scan |
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284 | instruction and used fewer cycles for memory accesses. |
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285 | |
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286 | If you are interested in knowing the worst case execution time for |
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287 | a particular version of RTEMS, please contact OAR Corporation and |
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288 | we will be happy to product the results as a consulting service. |
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289 | |
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290 | Non-maskable interrupts (NMI) cannot be disabled, and |
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291 | ISRs which execute at this level MUST NEVER issue RTEMS system |
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292 | calls. If a directive is invoked, unpredictable results may |
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293 | occur due to the inability of RTEMS to protect its critical |
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294 | sections. However, ISRs that make no system calls may safely |
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295 | execute as non-maskable interrupts. |
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296 | |
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297 | |
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298 | @c |
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299 | @c |
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300 | @c |
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301 | @section Default Fatal Error Processing |
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302 | |
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303 | Upon detection of a fatal error by either the application or RTEMS during |
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304 | initialization the @code{rtems_fatal_error_occurred} directive supplied |
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305 | by the Fatal Error Manager is invoked. The Fatal Error Manager will |
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306 | invoke the user-supplied fatal error handlers. If no user-supplied |
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307 | handlers are configured or all of them return without taking action to |
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308 | shutdown the processor or reset, a default fatal error handler is invoked. |
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309 | |
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310 | Most of the action performed as part of processing the fatal error are |
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311 | described in detail in the Fatal Error Manager chapter in the User's |
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312 | Guide. However, the if no user provided extension or BSP specific fatal |
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313 | error handler takes action, the final default action is to invoke a |
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314 | CPU architecture specific function. Typically this function disables |
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315 | interrupts and halts the processor. |
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316 | |
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317 | In each of the architecture specific chapters, this describes the precise |
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318 | operations of the default CPU specific fatal error handler. |
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319 | |
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320 | @c |
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321 | @c |
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322 | @c |
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323 | |
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324 | @section Board Support Packages |
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325 | |
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326 | An RTEMS Board Support Package (BSP) must be designed to support a |
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327 | particular processor model and target board combination. |
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328 | |
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329 | In each of the architecture specific chapters, this section will present |
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330 | a discussion of architecture specific BSP issues. For more information |
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331 | on developing a BSP, refer to BSP and Device Driver Development Guide |
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332 | and the chapter titled Board Support Packages in the RTEMS |
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333 | Applications User's Guide. |
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334 | |
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335 | @subsection System Reset |
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336 | |
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337 | An RTEMS based application is initiated or re-initiated when the processor |
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338 | is reset or transfer is passed to it from a boot monitor or ROM monitor. |
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339 | |
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340 | In each of the architecture specific chapters, this subsection describes |
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341 | the actions that the BSP must tak assuming the application gets control |
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342 | when the microprocessor is reset. |
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