1 | @c |
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2 | @c Copyright (c) 2015 University of York. |
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3 | @c Hesham ALMatary <hmka501@york.ac.uk> |
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4 | |
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5 | @ifinfo |
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6 | @end ifinfo |
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7 | @chapter Epiphany Specific Information |
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8 | |
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9 | This chapter discusses the |
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10 | @uref{http://adapteva.com/docs/epiphany_sdk_ref.pdf, Epiphany Architecture} |
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11 | dependencies in this port of RTEMS. Epiphany is a chip that can come with 16 and |
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12 | 64 cores, each of which can run RTEMS separately or they can work together to |
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13 | run a SMP RTEMS application. |
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14 | |
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15 | @subheading Architecture Documents |
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16 | |
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17 | For information on the Epiphany architecture refer to the |
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18 | @uref{http://adapteva.com/docs/epiphany_arch_ref.pdf,Epiphany Architecture Reference}. |
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19 | |
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20 | @section Calling Conventions |
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21 | |
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22 | Please refer to the |
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23 | @uref{http://adapteva.com/docs/epiphany_sdk_ref.pdf, Epiphany SDK} |
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24 | Appendix A: Application Binary Interface |
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25 | |
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26 | @subsection Floating Point Unit |
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27 | |
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28 | A floating point unit is currently not supported. |
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29 | |
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30 | @section Memory Model |
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31 | |
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32 | A flat 32-bit memory model is supported, no caches. Each core has its own 32 KiB |
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33 | strictly ordered local memory along with an access to a shared 32 MiB external |
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34 | DRAM. |
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35 | |
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36 | @section Interrupt Processing |
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37 | |
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38 | Every Epiphany core has 10 exception types: |
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39 | |
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40 | @itemize @bullet |
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41 | |
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42 | @item Reset |
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43 | @item Software Exception |
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44 | @item Data Page Fault |
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45 | @item Timer 0 |
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46 | @item Timer 1 |
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47 | @item Message Interrupt |
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48 | @item DMA0 Interrupt |
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49 | @item DMA1 Interrupt |
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50 | @item WANT Interrupt |
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51 | @item User Interrupt |
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52 | |
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53 | @end itemize |
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54 | |
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55 | @subsection Interrupt Levels |
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56 | |
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57 | There are only two levels: interrupts enabled and interrupts disabled. |
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58 | |
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59 | @subsection Interrupt Stack |
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60 | |
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61 | The Epiphany RTEMS port uses a dedicated software interrupt stack. |
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62 | The stack for interrupts is allocated during interrupt driver initialization. |
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63 | When an interrupt is entered, the _ISR_Handler routine is responsible for |
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64 | switching from the interrupted task stack to RTEMS software interrupt stack. |
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65 | |
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66 | @section Default Fatal Error Processing |
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67 | |
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68 | The default fatal error handler for this architecture performs the |
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69 | following actions: |
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70 | |
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71 | @itemize @bullet |
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72 | @item disables operating system supported interrupts (IRQ), |
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73 | @item places the error code in @code{r0}, and |
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74 | @item executes an infinite loop to simulate a halt processor instruction. |
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75 | @end itemize |
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76 | |
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77 | @section Symmetric Multiprocessing |
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78 | |
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79 | SMP is not supported. |
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