1 | @c |
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2 | @c COPYRIGHT (c) 1988-2006. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | |
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6 | @ifinfo |
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7 | @end ifinfo |
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8 | @chapter Blackfin Specific Information |
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9 | |
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10 | This chapter discusses the Blackfin architecture dependencies in this |
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11 | port of RTEMS. |
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12 | |
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13 | @subheading Architecture Documents |
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14 | |
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15 | For information on the Blackfin architecture, refer to the following |
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16 | documents available from Analog Devices. |
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17 | |
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18 | TBD |
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19 | |
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20 | @itemize @bullet |
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21 | @item @cite{"ADSP-BF533 Blackfin Processor Hardware Reference."} |
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22 | @file{http://www.analog.com/UploadedFiles/Associated_Docs/892485982bf533_hwr.pdf} |
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23 | |
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24 | @end itemize |
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25 | |
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26 | |
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27 | @section CPU Model Dependent Features |
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28 | |
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29 | CPUs of the Blackfin 53X only differ in the peripherals and thus in the |
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30 | device drivers. This port does not yet support the 56X dual core variants. |
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31 | |
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32 | @subsection Count Leading Zeroes Instruction |
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33 | |
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34 | The Blackfin CPU has the BITTST instruction which could be used to speed |
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35 | up the find first bit operation. The use of this instruction should |
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36 | significantly speed up the scheduling associated with a thread blocking. |
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37 | |
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38 | @section Calling Conventions |
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39 | |
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40 | This section is heavily based on content taken from the Blackfin uCLinux |
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41 | documentation wiki which is edited by Analog Devices and Arcturus |
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42 | Networks. @file{http://docs.blackfin.uclinux.org/} |
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43 | |
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44 | @subsection Processor Background |
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45 | |
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46 | The Blackfin architecture supports a simple call and return mechanism. |
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47 | A subroutine is invoked via the call (@code{call}) instruction. |
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48 | This instruction saves the return address in the @code{RETS} register |
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49 | and transfers the execution to the given address. |
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50 | |
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51 | It is the called funcions responsability to use the link instruction |
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52 | to reserve space on the stack for the local variables. Returning from |
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53 | a subroutine is done by using the RTS (@code{RTS}) instruction which |
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54 | loads the PC with the adress stored in RETS. |
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55 | |
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56 | It is is important to note that the @code{call} instruction does not |
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57 | automatically save or restore any registers. It is the responsibility |
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58 | of the high-level language compiler to define the register preservation |
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59 | and usage convention. |
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60 | |
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61 | @subsection Register Usage |
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62 | |
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63 | A called function may clobber all registers, except RETS, R4-R7, P3-P5, |
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64 | FP and SP. It may also modify the first 12 bytes in the callerâs stack |
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65 | frame which is used as an argument area for the first three arguments |
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66 | (which are passed in R0...R3 but may be placed on the stack by the |
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67 | called function). |
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68 | |
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69 | @subsection Parameter Passing |
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70 | |
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71 | RTEMS assumes that the Blackfin GCC calling convention is followed. |
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72 | The first three parameters are stored in registers R0, R1, and R2. |
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73 | All other parameters are put pushed on the stack. The result is returned |
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74 | through register R0. |
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75 | |
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76 | @section Memory Model |
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77 | |
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78 | The Blackfin family architecutre support a single unified 4 GB byte |
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79 | address space using 32-bit addresses. It maps all resources like internal |
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80 | and external memory and IO registers into separate sections of this |
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81 | common address space. |
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82 | |
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83 | The Blackfin architcture supports some form of memory |
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84 | protection via its Memory Management Unit. Since the |
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85 | Blackfin port runs in supervisior mode this memory |
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86 | protection mechanisms are not used. |
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87 | |
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88 | @section Interrupt Processing |
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89 | |
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90 | Discussed in this chapter are the Blackfin's interrupt response and |
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91 | control mechanisms as they pertain to RTEMS. The Blackfin architecture |
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92 | support 16 kinds of interrupts broken down into Core and general-purpose |
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93 | interrupts. |
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94 | |
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95 | @subsection Vectoring of an Interrupt Handler |
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96 | |
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97 | RTEMS maps levels 0 -15 directly to Blackfins event vectors EVT0 - |
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98 | EVT15. Since EVT0 - EVT6 are core events and it is suggested to use |
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99 | EVT15 and EVT15 for Software interrupts, 7 Interrupts (EVT7-EVT13) |
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100 | are left for periferical use. |
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101 | |
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102 | When installing an RTEMS interrupt handler RTEMS installs a generic |
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103 | Interrupt Handler which saves some context and enables nested interrupt |
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104 | servicing and then vectors to the users interrupt handler. |
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105 | |
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106 | @subsection Disabling of Interrupts by RTEMS |
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107 | |
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108 | During interrupt disable critical sections, RTEMS disables interrupts to |
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109 | level four (4) before the execution of this section and restores them |
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110 | to the previous level upon completion of the section. RTEMS uses the |
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111 | instructions CLI and STI to enable and disable Interrupts. Emulation, |
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112 | Reset, NMI and Exception Interrupts are never disabled. |
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113 | |
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114 | @subsection Interrupt Stack |
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115 | |
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116 | The Blackfin Architecture works with two different kind of stacks, |
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117 | User and Supervisor Stack. Since RTEMS and its Application run |
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118 | in supervisor mode, all interrupts will use the interrupted |
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119 | tasks stack for execution. |
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120 | |
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121 | @section Default Fatal Error Processing |
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122 | |
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123 | The default fatal error handler for the Blackfin performs the following |
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124 | actions: |
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125 | |
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126 | @itemize @bullet |
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127 | @item disables processor interrupts, |
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128 | @item places the error code in @b{r0}, and |
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129 | @item executes an infinite loop (@code{while(0);} to |
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130 | simulate a halt processor instruction. |
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131 | @end itemize |
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132 | |
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133 | @section Symmetric Multiprocessing |
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134 | |
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135 | SMP is not supported. |
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136 | |
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137 | @section Thread-Local Storage |
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138 | |
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139 | Thread-local storage is not implemented. |
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140 | |
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141 | @section Board Support Packages |
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142 | |
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143 | |
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144 | @subsection System Reset |
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145 | |
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146 | TBD |
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