source: rtems/doc/cpu_supplement/arm.t @ c9d0793

Last change on this file since c9d0793 was c9d0793, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 18, 2016 at 7:41:20 AM

doc: Update ARM floating-point support

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1@c
2@c  COPYRIGHT (c) 1988-2002.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5
6@ifinfo
7@end ifinfo
8@chapter ARM Specific Information
9
10This chapter discusses the
11@uref{http://en.wikipedia.org/wiki/ARM_architecture,ARM architecture}
12dependencies in this port of RTEMS.  The ARMv4T (and compatible), ARMv7-A,
13ARMv7-R and ARMv7-M architecture versions are supported by RTEMS.  Processors
14with a MMU use a static configuration which is set up during system start.  SMP
15is supported.
16
17@subheading Architecture Documents
18
19For information on the ARM architecture refer to the
20@uref{http://infocenter.arm.com,ARM Infocenter}.
21
22@section CPU Model Dependent Features
23
24This section presents the set of features which vary
25across ARM implementations and are of importance to RTEMS.  The set of CPU
26model feature macros are defined in the file
27@file{cpukit/score/cpu/arm/rtems/score/arm.h} based upon the particular CPU
28model flags specified on the compilation command line.
29
30@subsection CPU Model Name
31
32The macro @code{CPU_MODEL_NAME} is a string which designates
33the architectural level of this CPU model.  See in
34@file{cpukit/score/cpu/arm/rtems/score/arm.h} for the values.
35
36@subsection Count Leading Zeroes Instruction
37
38The ARMv5 and later has the count leading zeroes @code{clz} instruction which
39could be used to speed up the find first bit operation.  The use of this
40instruction should significantly speed up the scheduling associated with a
41thread blocking.  This is currently not used.
42
43@subsection Floating Point Unit
44
45The following floating point units are supported.
46
47@itemize @bullet
48
49@item VFPv3-D32/NEON (for example available on Cortex-A processors)
50@item VFPv3-D16 (for example available on Cortex-R processors)
51@item FPv4-SP-D16 (for example available on Cortex-M processors)
52@item FPv5-D16 (for example available the Cortex-M7 processor)
53
54@end itemize
55
56@c
57@c
58@c
59@section Multilibs
60
61The following multilibs are available:
62
63@enumerate
64@item @code{.}: ARMv4T, ARM instruction set
65@item @code{thumb}: ARMv4T, Thumb-1 instruction set
66@item @code{thumb/armv6-m}: ARMv6M, subset of Thumb-2 instruction set
67@item @code{thumb/armv7-a}: ARMv7-A, Thumb-2 instruction set
68@item @code{thumb/armv7-a/neon/hard}: ARMv7-A, Thumb-2 instruction set with
69hard-float ABI Neon and VFP-D32 support
70@item @code{thumb/armv7-r}: ARMv7-R, Thumb-2 instruction set
71@item @code{thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Thumb-2 instruction set
72with hard-float ABI VFP-D16 support
73@item @code{thumb/armv7-m}: ARMv7-M, Thumb-2 instruction set with hardware
74integer division (SDIV/UDIV)
75@item @code{thumb/armv7-m/fpv4-sp-d16}: ARMv7-M, Thumb-2 instruction set with
76hardware integer division (SDIV/UDIV) and hard-float ABI FPv4-SP support
77@item @code{thumb/cortex-m7/fpv5-d16}: ARMv7M, Thumb-2 instruction set
78optimized for Cortex-M7 with hard-float ABI VFP-D16 support and support for the
7964-bit floating point unit
80@item @code{eb/thumb/armv7-r}: ARMv7-R, Big-endian Thumb-2 instruction set
81@item @code{eb/thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Big-endian Thumb-2
82instruction set with hard-float ABI VFP-D16 support
83@end enumerate
84
85Multilib 1. and 2. support the standard ARM7TDMI and ARM926EJ-S targets.
86
87Multilib 3. supports the Cortex-M0 and Cortex-M1 cores.
88
89Multilib 8. supports the Cortex-M3, Cortex-M4 and Cortex-M7 cores, which have a
90special hardware integer division instruction (this is not present in the A and
91R profiles).
92
93Multilib 9. supports the Cortex-M4 cores with a floating point unit.
94
95Multilib 10. supports the Cortex-M7 core with a floating point unit.
96
97Multilib 4. and 5. support the Cortex-A processors.
98
99Multilib 6., 7., 11. and 12. support the Cortex-R processors.  Here also
100big-endian variants are available.
101
102Use for example the following GCC options
103
104@example
105-mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
106@end example
107
108to build an application or BSP for the ARMv7-A architecture and tune the code
109for a Cortex-A9 processor.  It is important to select the options used for the
110multilibs. For example
111
112@example
113-mthumb -mcpu=cortex-a9
114@end example
115
116alone will not select the ARMv7-A multilib.
117
118@section Calling Conventions
119
120Please refer to the
121@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf,Procedure Call Standard for the ARM Architecture}.
122
123@section Memory Model
124
125A flat 32-bit memory model is supported.  The board support package must take
126care about the MMU if necessary.
127
128@section Interrupt Processing
129
130The ARMv4T (and compatible) architecture has seven exception types:
131
132@itemize @bullet
133
134@item Reset
135@item Undefined
136@item Software Interrupt (SWI)
137@item Prefetch Abort
138@item Data Abort
139@item Interrupt (IRQ)
140@item Fast Interrupt (FIQ)
141
142@end itemize
143
144Of these types only the IRQ has explicit operating system support.  It is
145intentional that the FIQ is not supported by the operating system.  Without
146operating system support for the FIQ it is not necessary to disable them during
147critical sections of the system.
148
149The ARMv7-M architecture has a completely different exception model.  Here
150interrupts are disabled with a write of 0x80 to the @code{basepri_max}
151register.  This means that all exceptions and interrupts with a priority value
152of greater than or equal to 0x80 are disabled.  Thus exceptions and interrupts
153with a priority value of less than 0x80 are non-maskable with respect to the
154operating system and therefore must not use operating system services.  Several
155support libraries of chip vendors implicitly shift the priority value somehow
156before the value is written to the NVIC IPR register.  This can easily lead to
157confusion.
158
159@subsection Interrupt Levels
160
161There are exactly two interrupt levels on ARM with respect to RTEMS.  Level
162zero corresponds to interrupts enabled.  Level one corresponds to interrupts
163disabled.
164 
165@subsection Interrupt Stack
166
167The board support package must initialize the interrupt stack. The memory for
168the stacks is usually reserved in the linker script.
169
170@section Default Fatal Error Processing
171
172The default fatal error handler for this architecture performs the
173following actions:
174
175@itemize @bullet
176@item disables operating system supported interrupts (IRQ),
177@item places the error code in @code{r0}, and
178@item executes an infinite loop to simulate a halt processor instruction.
179@end itemize
180
181@section Symmetric Multiprocessing
182
183SMP is supported on ARMv7-A.  Available platforms are the Altera Cyclone V and
184the Xilinx Zynq.
185
186@section Thread-Local Storage
187
188Thread-local storage is supported.
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