source: rtems/doc/cpu_supplement/arm.t @ 48680277

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Last change on this file since 48680277 was 48680277, checked in by Sebastian Huber <sebastian.huber@…>, on 01/15/16 at 12:18:48

doc: Mention Cortex-M7 multilib

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1@c
2@c  COPYRIGHT (c) 1988-2002.
3@c  On-Line Applications Research Corporation (OAR).
4@c  All rights reserved.
5
6@ifinfo
7@end ifinfo
8@chapter ARM Specific Information
9
10This chapter discusses the
11@uref{http://en.wikipedia.org/wiki/ARM_architecture,ARM architecture}
12dependencies in this port of RTEMS.  The ARMv4T (and compatible), ARMv7-A,
13ARMv7-R and ARMv7-M architecture versions are supported by RTEMS.  Processors
14with a MMU use a static configuration which is set up during system start.  SMP
15is supported.
16
17@subheading Architecture Documents
18
19For information on the ARM architecture refer to the
20@uref{http://infocenter.arm.com,ARM Infocenter}.
21
22@section CPU Model Dependent Features
23
24This section presents the set of features which vary
25across ARM implementations and are of importance to RTEMS.  The set of CPU
26model feature macros are defined in the file
27@file{cpukit/score/cpu/arm/rtems/score/arm.h} based upon the particular CPU
28model flags specified on the compilation command line.
29
30@subsection CPU Model Name
31
32The macro @code{CPU_MODEL_NAME} is a string which designates
33the architectural level of this CPU model.  See in
34@file{cpukit/score/cpu/arm/rtems/score/arm.h} for the values.
35
36@subsection Count Leading Zeroes Instruction
37
38The ARMv5 and later has the count leading zeroes @code{clz} instruction which
39could be used to speed up the find first bit operation.  The use of this
40instruction should significantly speed up the scheduling associated with a
41thread blocking.  This is currently not used.
42
43@subsection Floating Point Unit
44
45The following floating point units are supported.
46
47@itemize @bullet
48
49@item VFPv3-D32/NEON (for example available on Cortex-A processors)
50@item VFPv3-D16 (for example available on Cortex-R processors)
51@item FPv4-SP-D16 (for example available on Cortex-M processors)
52
53@end itemize
54
55@c
56@c
57@c
58@section Multilibs
59
60The following multilibs are available:
61
62@enumerate
63@item @code{.}: ARMv4T, ARM instruction set
64@item @code{thumb}: ARMv4T, Thumb-1 instruction set
65@item @code{thumb/armv6-m}: ARMv6M, subset of Thumb-2 instruction set
66@item @code{thumb/armv7-a}: ARMv7-A, Thumb-2 instruction set
67@item @code{thumb/armv7-a/neon/hard}: ARMv7-A, Thumb-2 instruction set with
68hard-float ABI Neon and VFP-D32 support
69@item @code{thumb/armv7-r}: ARMv7-R, Thumb-2 instruction set
70@item @code{thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Thumb-2 instruction set
71with hard-float ABI VFP-D16 support
72@item @code{thumb/armv7-m}: ARMv7-M, Thumb-2 instruction set with hardware
73integer division (SDIV/UDIV)
74@item @code{thumb/armv7-m/fpv4-sp-d16}: ARMv7-M, Thumb-2 instruction set with
75hardware integer division (SDIV/UDIV) and hard-float ABI FPv4-SP support
76@item @code{thumb/cortex-m7/fpv5-d16}: ARMv7M, Thumb-2 instruction set
77optimized for Cortex-M7 with hard-float ABI VFP-D16 support and support for the
7864-bit floating point unit
79@item @code{eb/thumb/armv7-r}: ARMv7-R, Big-endian Thumb-2 instruction set
80@item @code{eb/thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Big-endian Thumb-2
81instruction set with hard-float ABI VFP-D16 support
82@end enumerate
83
84Multilib 1. and 2. support the standard ARM7TDMI and ARM926EJ-S targets.
85
86Multilib 3. supports the Cortex-M0 and Cortex-M1 cores.
87
88Multilib 8. supports the Cortex-M3, Cortex-M4 and Cortex-M7 cores, which have a
89special hardware integer division instruction (this is not present in the A and
90R profiles).
91
92Multilib 9. supports the Cortex-M4 cores with a floating point unit.
93
94Multilib 10. supports the Cortex-M7 core with a floating point unit.
95
96Multilib 4. and 5. support the Cortex-A processors.
97
98Multilib 6., 7., 11. and 12. support the Cortex-R processors.  Here also
99big-endian variants are available.
100
101Use for example the following GCC options
102
103@example
104-mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9
105@end example
106
107to build an application or BSP for the ARMv7-A architecture and tune the code
108for a Cortex-A9 processor.  It is important to select the options used for the
109multilibs. For example
110
111@example
112-mthumb -mcpu=cortex-a9
113@end example
114
115alone will not select the ARMv7-A multilib.
116
117@section Calling Conventions
118
119Please refer to the
120@uref{http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf,Procedure Call Standard for the ARM Architecture}.
121
122@section Memory Model
123
124A flat 32-bit memory model is supported.  The board support package must take
125care about the MMU if necessary.
126
127@section Interrupt Processing
128
129The ARMv4T (and compatible) architecture has seven exception types:
130
131@itemize @bullet
132
133@item Reset
134@item Undefined
135@item Software Interrupt (SWI)
136@item Prefetch Abort
137@item Data Abort
138@item Interrupt (IRQ)
139@item Fast Interrupt (FIQ)
140
141@end itemize
142
143Of these types only the IRQ has explicit operating system support.  It is
144intentional that the FIQ is not supported by the operating system.  Without
145operating system support for the FIQ it is not necessary to disable them during
146critical sections of the system.
147
148The ARMv7-M architecture has a completely different exception model.  Here
149interrupts are disabled with a write of 0x80 to the @code{basepri_max}
150register.  This means that all exceptions and interrupts with a priority value
151of greater than or equal to 0x80 are disabled.  Thus exceptions and interrupts
152with a priority value of less than 0x80 are non-maskable with respect to the
153operating system and therefore must not use operating system services.  Several
154support libraries of chip vendors implicitly shift the priority value somehow
155before the value is written to the NVIC IPR register.  This can easily lead to
156confusion.
157
158@subsection Interrupt Levels
159
160There are exactly two interrupt levels on ARM with respect to RTEMS.  Level
161zero corresponds to interrupts enabled.  Level one corresponds to interrupts
162disabled.
163 
164@subsection Interrupt Stack
165
166The board support package must initialize the interrupt stack. The memory for
167the stacks is usually reserved in the linker script.
168
169@section Default Fatal Error Processing
170
171The default fatal error handler for this architecture performs the
172following actions:
173
174@itemize @bullet
175@item disables operating system supported interrupts (IRQ),
176@item places the error code in @code{r0}, and
177@item executes an infinite loop to simulate a halt processor instruction.
178@end itemize
179
180@section Symmetric Multiprocessing
181
182SMP is supported on ARMv7-A.  Available platforms are the Altera Cyclone V and
183the Xilinx Zynq.
184
185@section Thread-Local Storage
186
187Thread-local storage is supported.
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