1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | |
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6 | @ifinfo |
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7 | @end ifinfo |
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8 | @chapter ARM Specific Information |
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9 | |
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10 | This chapter discusses the |
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11 | @uref{http://en.wikipedia.org/wiki/ARM_architecture,ARM architecture} |
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12 | dependencies in this port of RTEMS. The ARMv4T (and compatible), ARMv7-A, |
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13 | ARMv7-R and ARMv7-M architecture versions are supported by RTEMS. Processors |
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14 | with a MMU use a static configuration which is set up during system start. SMP |
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15 | is supported. |
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16 | |
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17 | @subheading Architecture Documents |
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18 | |
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19 | For information on the ARM architecture refer to the |
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20 | @uref{http://infocenter.arm.com,ARM Infocenter}. |
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21 | |
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22 | @section CPU Model Dependent Features |
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23 | |
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24 | This section presents the set of features which vary |
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25 | across ARM implementations and are of importance to RTEMS. The set of CPU |
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26 | model feature macros are defined in the file |
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27 | @file{cpukit/score/cpu/arm/rtems/score/arm.h} based upon the particular CPU |
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28 | model flags specified on the compilation command line. |
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29 | |
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30 | @subsection CPU Model Name |
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31 | |
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32 | The macro @code{CPU_MODEL_NAME} is a string which designates |
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33 | the architectural level of this CPU model. See in |
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34 | @file{cpukit/score/cpu/arm/rtems/score/arm.h} for the values. |
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35 | |
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36 | @subsection Count Leading Zeroes Instruction |
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37 | |
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38 | The ARMv5 and later has the count leading zeroes @code{clz} instruction which |
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39 | could be used to speed up the find first bit operation. The use of this |
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40 | instruction should significantly speed up the scheduling associated with a |
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41 | thread blocking. This is currently not used. |
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42 | |
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43 | @subsection Floating Point Unit |
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44 | |
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45 | The following floating point units are supported. |
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46 | |
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47 | @itemize @bullet |
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48 | |
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49 | @item VFPv3-D32/NEON (for example available on Cortex-A processors) |
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50 | @item VFPv3-D16 (for example available on Cortex-R processors) |
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51 | @item FPv4-SP-D16 (for example available on Cortex-M processors) |
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52 | |
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53 | @end itemize |
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54 | |
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55 | @c |
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56 | @c |
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57 | @c |
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58 | @section Multilibs |
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59 | |
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60 | The following multilibs are available: |
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61 | |
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62 | @enumerate |
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63 | @item @code{.}: ARMv4T, ARM instruction set |
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64 | @item @code{thumb}: ARMv4T, Thumb-1 instruction set |
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65 | @item @code{thumb/armv6-m}: ARMv6M, subset of Thumb-2 instruction set |
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66 | @item @code{thumb/armv7-a}: ARMv7-A, Thumb-2 instruction set |
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67 | @item @code{thumb/armv7-a/neon/hard}: ARMv7-A, Thumb-2 instruction set with |
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68 | hard-float ABI Neon and VFP-D32 support |
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69 | @item @code{thumb/armv7-r}: ARMv7-R, Thumb-2 instruction set |
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70 | @item @code{thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Thumb-2 instruction set |
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71 | with hard-float ABI VFP-D16 support |
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72 | @item @code{thumb/armv7-m}: ARMv7-M, Thumb-2 instruction set with hardware |
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73 | integer division (SDIV/UDIV) |
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74 | @item @code{thumb/armv7-m/fpv4-sp-d16}: ARMv7-M, Thumb-2 instruction set with |
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75 | hardware integer division (SDIV/UDIV) and hard-float ABI FPv4-SP support |
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76 | @item @code{eb/thumb/armv7-r}: ARMv7-R, Big-endian Thumb-2 instruction set |
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77 | @item @code{eb/thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Big-endian Thumb-2 |
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78 | instruction set with hard-float ABI VFP-D16 support |
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79 | @end enumerate |
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80 | |
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81 | Multilib 1. and 2. support the standard ARM7TDMI and ARM926EJ-S targets. |
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82 | |
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83 | Multilib 3. supports the Cortex-M0 and Cortex-M1 cores. |
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84 | |
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85 | Multilib 8. supports the Cortex-M3 and Cortex-M4 cores, which have a special |
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86 | hardware integer division instruction (this is not present in the A and R |
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87 | profiles). |
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88 | |
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89 | Multilib 9. supports the Cortex-M4 cores with a floating point unit. |
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90 | |
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91 | Multilib 4. and 5. support the Cortex-A processors. |
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92 | |
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93 | Multilib 6., 7., 10. and 11. support the Cortex-R processors. Here also |
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94 | big-endian variants are available. |
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95 | |
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96 | Use for example the following GCC options |
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97 | |
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98 | @example |
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99 | -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 |
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100 | @end example |
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101 | |
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102 | to build an application or BSP for the ARMv7-A architecture and tune the code |
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103 | for a Cortex-A9 processor. It is important to select the options used for the |
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104 | multilibs. For example |
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105 | |
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106 | @example |
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107 | -mthumb -mcpu=cortex-a9 |
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108 | @end example |
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109 | |
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110 | alone will not select the ARMv7-A multilib. |
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111 | |
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112 | @section Calling Conventions |
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113 | |
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114 | Please refer to the |
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115 | @uref{http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042c/IHI0042C_aapcs.pdf,Procedure Call Standard for the ARM Architecture}. |
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116 | |
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117 | @section Memory Model |
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118 | |
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119 | A flat 32-bit memory model is supported. The board support package must take |
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120 | care about the MMU if necessary. |
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121 | |
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122 | @section Interrupt Processing |
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123 | |
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124 | The ARMv4T (and compatible) architecture has seven exception types: |
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125 | |
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126 | @itemize @bullet |
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127 | |
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128 | @item Reset |
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129 | @item Undefined |
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130 | @item Software Interrupt (SWI) |
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131 | @item Prefetch Abort |
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132 | @item Data Abort |
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133 | @item Interrupt (IRQ) |
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134 | @item Fast Interrupt (FIQ) |
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135 | |
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136 | @end itemize |
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137 | |
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138 | Of these types only the IRQ has explicit operating system support. It is |
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139 | intentional that the FIQ is not supported by the operating system. Without |
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140 | operating system support for the FIQ it is not necessary to disable them during |
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141 | critical sections of the system. |
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142 | |
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143 | The ARMv7-M architecture has a completely different exception model. Here |
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144 | interrupts are disabled with a write of 0x80 to the @code{basepri_max} |
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145 | register. This means that all exceptions and interrupts with a priority value |
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146 | of greater than or equal to 0x80 are disabled. Thus exceptions and interrupts |
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147 | with a priority value of less than 0x80 are non-maskable with respect to the |
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148 | operating system and therefore must not use operating system services. Several |
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149 | support libraries of chip vendors implicitly shift the priority value somehow |
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150 | before the value is written to the NVIC IPR register. This can easily lead to |
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151 | confusion. |
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152 | |
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153 | @subsection Interrupt Levels |
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154 | |
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155 | There are exactly two interrupt levels on ARM with respect to RTEMS. Level |
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156 | zero corresponds to interrupts enabled. Level one corresponds to interrupts |
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157 | disabled. |
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158 | |
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159 | @subsection Interrupt Stack |
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160 | |
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161 | The board support package must initialize the interrupt stack. The memory for |
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162 | the stacks is usually reserved in the linker script. |
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163 | |
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164 | @section Default Fatal Error Processing |
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165 | |
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166 | The default fatal error handler for this architecture performs the |
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167 | following actions: |
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168 | |
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169 | @itemize @bullet |
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170 | @item disables operating system supported interrupts (IRQ), |
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171 | @item places the error code in @code{r0}, and |
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172 | @item executes an infinite loop to simulate a halt processor instruction. |
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173 | @end itemize |
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174 | |
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175 | @section Symmetric Multiprocessing |
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176 | |
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177 | SMP is supported on ARMv7-A. Available platforms are the Altera Cyclone V and |
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178 | the Xilinx Zynq. |
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179 | |
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180 | @section Thread-Local Storage |
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181 | |
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182 | Thread-local storage is supported. |
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