1 | @c |
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2 | @c COPYRIGHT (c) 1988-2002. |
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3 | @c On-Line Applications Research Corporation (OAR). |
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4 | @c All rights reserved. |
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5 | @c |
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6 | @c $Id$ |
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7 | @c |
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8 | |
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9 | @chapter Shared Memory Support Driver |
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10 | |
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11 | The Shared Memory Support Driver is responsible for providing glue |
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12 | routines and configuration information required by the Shared |
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13 | Memory Multiprocessor Communications Interface (MPCI). The |
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14 | Shared Memory Support Driver tailors the portable Shared |
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15 | Memory Driver to a particular target platform. |
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16 | |
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17 | This driver is only required in shared memory multiprocessing |
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18 | systems that use the RTEMS mulitprocessing support. For more |
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19 | information on RTEMS multiprocessing capabilities and the |
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20 | MPCI, refer to the @b{Multiprocessing Manager} chapter |
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21 | of the @b{RTEMS Application C User's Guide}. |
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22 | |
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23 | @section Shared Memory Configuration Table |
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24 | |
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25 | The Shared Memory Configuration Table is defined in the following |
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26 | structure: |
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27 | |
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28 | @example |
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29 | @group |
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30 | typedef volatile rtems_unsigned32 vol_u32; |
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31 | |
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32 | typedef struct @{ |
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33 | vol_u32 *address; /* write here for interrupt */ |
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34 | vol_u32 value; /* this value causes interrupt */ |
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35 | vol_u32 length; /* for this length (0,1,2,4) */ |
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36 | @} Shm_Interrupt_information; |
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37 | |
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38 | struct shm_config_info @{ |
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39 | vol_u32 *base; /* base address of SHM */ |
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40 | vol_u32 length; /* length (in bytes) of SHM */ |
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41 | vol_u32 format; /* SHM is big or little endian */ |
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42 | vol_u32 (*convert)(); /* neutral conversion routine */ |
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43 | vol_u32 poll_intr; /* POLLED or INTR driven mode */ |
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44 | void (*cause_intr)( rtems_unsigned32 ); |
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45 | Shm_Interrupt_information Intr; /* cause intr information */ |
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46 | @}; |
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47 | |
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48 | typedef struct shm_config_info shm_config_table; |
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49 | @end group |
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50 | @end example |
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51 | |
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52 | where the fields are defined as follows: |
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53 | |
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54 | @table @b |
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55 | @item base |
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56 | is the base address of the shared memory buffer used to pass |
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57 | messages between the nodes in the system. |
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58 | |
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59 | @item length |
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60 | is the length (in bytes) of the shared memory buffer used to pass |
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61 | messages between the nodes in the system. |
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62 | |
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63 | @item format |
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64 | is either SHM_BIG or SHM_LITTLE to indicate that the neutral format |
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65 | of the shared memory area is big or little endian. The format |
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66 | of the memory should be chosen to match most of the inter-node traffic. |
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67 | |
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68 | @item convert |
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69 | is the address of a routine which converts from native format to |
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70 | neutral format. Ideally, the neutral format is the same as the |
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71 | native format so this routine is quite simple. |
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72 | |
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73 | @item poll_intr |
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74 | is either INTR_MODE or POLLED_MODE to indicate how the node will be |
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75 | informed of incoming messages. |
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76 | |
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77 | @item cause_intr |
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78 | |
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79 | @item Intr |
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80 | is the information required to cause an interrupt on a node. This |
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81 | structure contains the following fields: |
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82 | @table @b |
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83 | @item address |
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84 | is the address to write at to cause an interrupt on that node. |
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85 | For a polled node, this should be NULL. |
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86 | |
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87 | @item value |
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88 | is the value to write to cause an interrupt. |
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89 | |
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90 | @item length |
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91 | is the length of the entity to write on the node to cause an interrupt. |
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92 | This can be 0 to indicate polled operation, 1 to write a byte, 2 to |
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93 | write a sixteen-bit entity, and 4 to write a thirty-two bit entity. |
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94 | @end table |
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95 | @end table |
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96 | |
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97 | @section Primitives |
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98 | |
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99 | @subsection Convert Address |
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100 | |
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101 | The @code{Shm_Convert_address} is responsible for converting an address |
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102 | of an entity in the shared memory area into the address that should be |
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103 | used from this node. Most targets will simply return the address |
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104 | passed to this routine. However, some target boards will have a special |
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105 | window onto the shared memory. For example, some VMEbus boards have |
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106 | special address windows to access addresses that are normally reserved |
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107 | in the CPU's address space. |
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108 | |
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109 | @example |
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110 | @group |
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111 | void *Shm_Convert_address( void *address ) |
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112 | @{ |
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113 | return the local address version of this bus address |
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114 | @} |
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115 | @end group |
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116 | @end example |
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117 | |
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118 | @subsection Get Configuration |
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119 | |
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120 | The @code{Shm_Get_configuration} routine is responsible for filling in the |
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121 | Shared Memory Configuration Table passed to it. |
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122 | |
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123 | @example |
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124 | @group |
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125 | void Shm_Get_configuration( |
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126 | rtems_unsigned32 localnode, |
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127 | shm_config_table **shmcfg |
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128 | ) |
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129 | @{ |
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130 | fill in the Shared Memory Configuration Table |
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131 | @} |
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132 | @end group |
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133 | @end example |
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134 | |
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135 | @subsection Locking Primitives |
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136 | |
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137 | This is a collection of routines that are invoked by the portable |
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138 | part of the Shared Memory Driver to manage locks in the shared |
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139 | memory buffer area. Accesses to the shared memory must be |
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140 | atomic. Two nodes in a multiprocessor system must not be manipulating |
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141 | the shared data structures simultaneously. The locking primitives |
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142 | are used to insure this. |
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143 | |
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144 | To avoid deadlock, local processor interrupts should be disabled the entire |
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145 | time the locked queue is locked. |
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146 | |
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147 | The locking primitives operate on the lock |
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148 | @code{field} of the @code{Shm_Locked_queue_Control} |
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149 | data structure. This structure is defined as follows: |
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150 | |
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151 | @example |
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152 | @group |
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153 | typedef struct @{ |
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154 | vol_u32 lock; /* lock field for this queue */ |
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155 | vol_u32 front; /* first envelope on queue */ |
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156 | vol_u32 rear; /* last envelope on queue */ |
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157 | vol_u32 owner; /* receiving (i.e. owning) node */ |
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158 | @} Shm_Locked_queue_Control; |
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159 | @end group |
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160 | @end example |
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161 | |
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162 | where each field is defined as follows: |
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163 | |
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164 | @table @b |
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165 | @item lock |
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166 | is the lock field. Every node in the system must agree on how this |
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167 | field will be used. Many processor families provide an atomic |
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168 | "test and set" instruction that is used to manage this field. |
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169 | |
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170 | @item front |
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171 | is the index of the first message on this locked queue. |
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172 | |
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173 | @item rear |
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174 | is the index of the last message on this locked queue. |
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175 | |
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176 | @item owner |
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177 | is the node number of the node that currently has this structure locked. |
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178 | |
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179 | @end table |
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180 | |
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181 | @subsubsection Initializing a Shared Lock |
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182 | |
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183 | The @code{Shm_Initialize_lock} routine is responsible for |
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184 | initializing the lock field. This routines usually is implemented |
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185 | as follows: |
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186 | |
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187 | @example |
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188 | @group |
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189 | void Shm_Initialize_lock( |
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190 | Shm_Locked_queue_Control *lq_cb |
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191 | ) |
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192 | @{ |
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193 | lq_cb->lock = LQ_UNLOCKED; |
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194 | @} |
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195 | @end group |
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196 | @end example |
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197 | |
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198 | @subsubsection Acquiring a Shared Lock |
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199 | |
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200 | The @code{Shm_Lock} routine is responsible for |
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201 | acquiring the lock field. Interrupts should be |
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202 | disabled while that lock is acquired. If the lock |
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203 | is currently unavailble, then the locking routine |
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204 | should delay a few microseconds to allow the other |
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205 | node to release the lock. Doing this reduces bus contention |
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206 | for the lock. This routines usually is implemented as follows: |
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207 | |
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208 | @example |
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209 | @group |
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210 | void Shm_Lock( |
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211 | Shm_Locked_queue_Control *lq_cb |
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212 | ) |
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213 | @{ |
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214 | disable processor interrupts |
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215 | set Shm_isrstat to previous interrupt disable level |
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216 | |
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217 | while ( TRUE ) @{ |
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218 | atomically attempt to acquire the lock |
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219 | if the lock was acquired |
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220 | return |
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221 | delay some small period of time |
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222 | @} |
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223 | @} |
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224 | @end group |
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225 | @end example |
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226 | |
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227 | @subsubsection Releasing a Shared Lock |
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228 | |
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229 | The @code{Shm_Unlock} routine is responsible for |
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230 | releasing the lock field and reenabling processor |
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231 | interrupts. This routines usually is implemented as follows: |
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232 | |
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233 | @example |
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234 | @group |
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235 | void Shm_Unlock( |
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236 | Shm_Locked_queue_Control *lq_cb |
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237 | ) |
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238 | @{ |
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239 | set the lock to the unlocked value |
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240 | reenable processor interrupts to their level prior |
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241 | to the lock being acquired. This value was saved |
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242 | in the global variable Shm_isrstat |
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243 | @} |
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244 | @end group |
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245 | @end example |
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246 | |
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247 | @section Installing the MPCI ISR |
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248 | |
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249 | The @code{Shm_setvec} is invoked by the portable portion |
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250 | of the shared memory to install the interrupt service routine |
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251 | that is invoked when an incoming message is announced. Some |
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252 | target boards support an interprocessor interrupt or mailbox |
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253 | scheme and this is where the ISR for that interrupt would be |
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254 | installed. |
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255 | |
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256 | On an interrupt driven node, this routine would be implemented |
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257 | as follows: |
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258 | |
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259 | @example |
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260 | @group |
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261 | void Shm_setvec( void ) |
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262 | @{ |
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263 | install the interprocessor communications ISR |
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264 | @} |
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265 | @end group |
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266 | @end example |
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267 | |
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268 | On a polled node, this routine would be empty. |
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269 | |
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