source: rtems/cpukit/score/src/threaddispatchdisablelevel.c @ d19cce29

4.115
Last change on this file since d19cce29 was d19cce29, checked in by Sebastian Huber <sebastian.huber@…>, on 08/05/13 at 12:54:11

score: Per-CPU thread dispatch disable level

Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.

The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().

The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).

As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().

A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.

All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).

  • Property mode set to 100644
File size: 3.6 KB
Line 
1/**
2 * @file
3 *
4 * @brief Thread Dispatch Disable Functions
5 *
6 * @ingroup ScoreThread
7 */
8
9/*
10 *  COPYRIGHT (c) 1989-2011.
11 *  On-Line Applications Research Corporation (OAR).
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.com/license/LICENSE.
16 */
17
18#include <rtems/score/threaddispatch.h>
19#include <rtems/score/assert.h>
20
21#define NO_OWNER_CPU 0xffffffffU
22
23typedef struct {
24  SMP_lock_Control lock;
25  uint32_t owner_cpu;
26  uint32_t nest_level;
27} Giant_Control;
28
29static Giant_Control _Giant = {
30  .lock = SMP_LOCK_INITIALIZER,
31  .owner_cpu = NO_OWNER_CPU,
32  .nest_level = 0
33};
34
35static void _Giant_Do_acquire( uint32_t self_cpu_index )
36{
37  Giant_Control *giant = &_Giant;
38
39  if ( giant->owner_cpu != self_cpu_index ) {
40    _SMP_lock_Acquire( &giant->lock );
41    giant->owner_cpu = self_cpu_index;
42    giant->nest_level = 1;
43  } else {
44    ++giant->nest_level;
45  }
46}
47
48static void _Giant_Do_release( void )
49{
50  Giant_Control *giant = &_Giant;
51
52  --giant->nest_level;
53  if ( giant->nest_level == 0 ) {
54    giant->owner_cpu = NO_OWNER_CPU;
55    _SMP_lock_Release( &giant->lock );
56  }
57}
58
59uint32_t _Thread_Dispatch_increment_disable_level( void )
60{
61  Giant_Control *giant = &_Giant;
62  ISR_Level isr_level;
63  uint32_t self_cpu_index;
64  uint32_t disable_level;
65  Per_CPU_Control *self_cpu;
66
67  _ISR_Disable( isr_level );
68
69  /*
70   * We must obtain the processor ID after interrupts are disabled to prevent
71   * thread migration.
72   */
73  self_cpu_index = _SMP_Get_current_processor();
74
75  _Giant_Do_acquire( self_cpu_index );
76
77  self_cpu = _Per_CPU_Get_by_index( self_cpu_index );
78  disable_level = self_cpu->thread_dispatch_disable_level;
79  ++disable_level;
80  self_cpu->thread_dispatch_disable_level = disable_level;
81
82  _ISR_Enable( isr_level );
83
84  return disable_level;
85}
86
87uint32_t _Thread_Dispatch_decrement_disable_level( void )
88{
89  ISR_Level isr_level;
90  uint32_t disable_level;
91  Per_CPU_Control *self_cpu;
92
93  _ISR_Disable( isr_level );
94
95  self_cpu = _Per_CPU_Get();
96  disable_level = self_cpu->thread_dispatch_disable_level;
97  --disable_level;
98  self_cpu->thread_dispatch_disable_level = disable_level;
99
100  _Giant_Do_release();
101
102  _ISR_Enable( isr_level );
103
104  return disable_level;
105}
106
107
108/*
109 * Note this method is taking a heavy handed approach to
110 * setting the dispatch level. This may be optimized at a
111 * later timee, but it must be in such a way that the nesting
112 * level is decremented by the same number as the dispatch level.
113 * This approach is safest until we are sure the nested spinlock
114 * is successfully working with smp isr source code. 
115 */
116
117uint32_t _Thread_Dispatch_set_disable_level(uint32_t value)
118{
119  ISR_Level isr_level;
120  uint32_t disable_level;
121
122  _ISR_Disable( isr_level );
123  disable_level = _Thread_Dispatch_disable_level;
124  _ISR_Enable( isr_level );
125
126  /*
127   * If we need the dispatch level to go higher
128   * call increment method the desired number of times.
129   */
130
131  while ( value > disable_level ) {
132    disable_level = _Thread_Dispatch_increment_disable_level();
133  }
134
135  /*
136   * If we need the dispatch level to go lower
137   * call increment method the desired number of times.
138   */
139
140  while ( value < disable_level ) {
141    disable_level = _Thread_Dispatch_decrement_disable_level();
142  }
143
144  return value;
145}
146
147void _Giant_Acquire( void )
148{
149  ISR_Level isr_level;
150
151  _ISR_Disable( isr_level );
152  _Assert( _Thread_Dispatch_disable_level != 0 );
153  _Giant_Do_acquire( _SMP_Get_current_processor() );
154  _ISR_Enable( isr_level );
155}
156
157void _Giant_Release( void )
158{
159  ISR_Level isr_level;
160
161  _ISR_Disable( isr_level );
162  _Assert( _Thread_Dispatch_disable_level != 0 );
163  _Giant_Do_release();
164  _ISR_Enable( isr_level );
165}
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