1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Thread Dispatch Disable Functions |
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5 | * |
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6 | * @ingroup ScoreThread |
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7 | */ |
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8 | |
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9 | /* |
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10 | * COPYRIGHT (c) 1989-2011. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | */ |
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17 | |
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18 | #include <rtems/score/threaddispatch.h> |
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19 | #include <rtems/score/assert.h> |
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20 | |
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21 | #define NO_OWNER_CPU 0xffffffffU |
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22 | |
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23 | typedef struct { |
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24 | SMP_lock_Control lock; |
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25 | uint32_t owner_cpu; |
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26 | uint32_t nest_level; |
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27 | } Giant_Control; |
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28 | |
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29 | static Giant_Control _Giant = { |
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30 | .lock = SMP_LOCK_INITIALIZER, |
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31 | .owner_cpu = NO_OWNER_CPU, |
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32 | .nest_level = 0 |
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33 | }; |
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34 | |
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35 | static void _Giant_Do_acquire( uint32_t self_cpu_index ) |
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36 | { |
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37 | Giant_Control *giant = &_Giant; |
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38 | |
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39 | if ( giant->owner_cpu != self_cpu_index ) { |
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40 | _SMP_lock_Acquire( &giant->lock ); |
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41 | giant->owner_cpu = self_cpu_index; |
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42 | giant->nest_level = 1; |
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43 | } else { |
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44 | ++giant->nest_level; |
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45 | } |
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46 | } |
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47 | |
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48 | static void _Giant_Do_release( void ) |
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49 | { |
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50 | Giant_Control *giant = &_Giant; |
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51 | |
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52 | --giant->nest_level; |
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53 | if ( giant->nest_level == 0 ) { |
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54 | giant->owner_cpu = NO_OWNER_CPU; |
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55 | _SMP_lock_Release( &giant->lock ); |
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56 | } |
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57 | } |
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58 | |
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59 | uint32_t _Thread_Dispatch_increment_disable_level( void ) |
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60 | { |
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61 | ISR_Level isr_level; |
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62 | uint32_t self_cpu_index; |
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63 | uint32_t disable_level; |
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64 | Per_CPU_Control *self_cpu; |
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65 | |
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66 | _ISR_Disable( isr_level ); |
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67 | |
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68 | /* |
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69 | * We must obtain the processor ID after interrupts are disabled to prevent |
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70 | * thread migration. |
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71 | */ |
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72 | self_cpu_index = _SMP_Get_current_processor(); |
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73 | |
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74 | _Giant_Do_acquire( self_cpu_index ); |
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75 | |
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76 | self_cpu = _Per_CPU_Get_by_index( self_cpu_index ); |
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77 | disable_level = self_cpu->thread_dispatch_disable_level; |
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78 | ++disable_level; |
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79 | self_cpu->thread_dispatch_disable_level = disable_level; |
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80 | |
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81 | _ISR_Enable( isr_level ); |
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82 | |
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83 | return disable_level; |
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84 | } |
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85 | |
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86 | uint32_t _Thread_Dispatch_decrement_disable_level( void ) |
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87 | { |
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88 | ISR_Level isr_level; |
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89 | uint32_t disable_level; |
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90 | Per_CPU_Control *self_cpu; |
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91 | |
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92 | _ISR_Disable( isr_level ); |
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93 | |
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94 | self_cpu = _Per_CPU_Get(); |
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95 | disable_level = self_cpu->thread_dispatch_disable_level; |
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96 | --disable_level; |
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97 | self_cpu->thread_dispatch_disable_level = disable_level; |
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98 | |
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99 | _Giant_Do_release(); |
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100 | |
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101 | _ISR_Enable( isr_level ); |
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102 | |
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103 | return disable_level; |
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104 | } |
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105 | |
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106 | |
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107 | /* |
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108 | * Note this method is taking a heavy handed approach to |
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109 | * setting the dispatch level. This may be optimized at a |
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110 | * later timee, but it must be in such a way that the nesting |
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111 | * level is decremented by the same number as the dispatch level. |
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112 | * This approach is safest until we are sure the nested spinlock |
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113 | * is successfully working with smp isr source code. |
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114 | */ |
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115 | |
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116 | uint32_t _Thread_Dispatch_set_disable_level(uint32_t value) |
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117 | { |
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118 | ISR_Level isr_level; |
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119 | uint32_t disable_level; |
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120 | |
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121 | _ISR_Disable( isr_level ); |
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122 | disable_level = _Thread_Dispatch_disable_level; |
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123 | _ISR_Enable( isr_level ); |
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124 | |
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125 | /* |
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126 | * If we need the dispatch level to go higher |
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127 | * call increment method the desired number of times. |
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128 | */ |
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129 | |
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130 | while ( value > disable_level ) { |
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131 | disable_level = _Thread_Dispatch_increment_disable_level(); |
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132 | } |
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133 | |
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134 | /* |
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135 | * If we need the dispatch level to go lower |
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136 | * call increment method the desired number of times. |
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137 | */ |
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138 | |
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139 | while ( value < disable_level ) { |
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140 | disable_level = _Thread_Dispatch_decrement_disable_level(); |
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141 | } |
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142 | |
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143 | return value; |
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144 | } |
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145 | |
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146 | void _Giant_Acquire( void ) |
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147 | { |
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148 | ISR_Level isr_level; |
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149 | |
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150 | _ISR_Disable( isr_level ); |
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151 | _Assert( _Thread_Dispatch_disable_level != 0 ); |
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152 | _Giant_Do_acquire( _SMP_Get_current_processor() ); |
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153 | _ISR_Enable( isr_level ); |
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154 | } |
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155 | |
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156 | void _Giant_Release( void ) |
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157 | { |
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158 | ISR_Level isr_level; |
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159 | |
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160 | _ISR_Disable( isr_level ); |
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161 | _Assert( _Thread_Dispatch_disable_level != 0 ); |
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162 | _Giant_Do_release(); |
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163 | _ISR_Enable( isr_level ); |
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164 | } |
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