1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Dispatch Thread |
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5 | * @ingroup ScoreThread |
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6 | */ |
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7 | |
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8 | /* |
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9 | * COPYRIGHT (c) 1989-2009. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * Copyright (c) 2014 embedded brains GmbH. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #if HAVE_CONFIG_H |
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20 | #include "config.h" |
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21 | #endif |
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22 | |
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23 | #include <rtems/score/threaddispatch.h> |
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24 | #include <rtems/score/apiext.h> |
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25 | #include <rtems/score/assert.h> |
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26 | #include <rtems/score/isr.h> |
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27 | #include <rtems/score/threadimpl.h> |
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28 | #include <rtems/score/todimpl.h> |
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29 | #include <rtems/score/userextimpl.h> |
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30 | #include <rtems/score/wkspace.h> |
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31 | #include <rtems/config.h> |
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32 | |
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33 | static Thread_Action *_Thread_Get_post_switch_action( |
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34 | Thread_Control *executing |
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35 | ) |
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36 | { |
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37 | Chain_Control *chain = &executing->Post_switch_actions.Chain; |
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38 | |
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39 | return (Thread_Action *) _Chain_Get_unprotected( chain ); |
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40 | } |
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41 | |
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42 | static void _Thread_Run_post_switch_actions( Thread_Control *executing ) |
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43 | { |
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44 | ISR_Level level; |
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45 | Per_CPU_Control *cpu_self; |
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46 | Thread_Action *action; |
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47 | |
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48 | cpu_self = _Thread_Action_ISR_disable_and_acquire( executing, &level ); |
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49 | action = _Thread_Get_post_switch_action( executing ); |
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50 | |
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51 | while ( action != NULL ) { |
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52 | _Chain_Set_off_chain( &action->Node ); |
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53 | |
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54 | ( *action->handler )( executing, action, cpu_self, level ); |
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55 | |
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56 | cpu_self = _Thread_Action_ISR_disable_and_acquire( executing, &level ); |
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57 | action = _Thread_Get_post_switch_action( executing ); |
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58 | } |
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59 | |
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60 | _Thread_Action_release_and_ISR_enable( cpu_self, level ); |
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61 | } |
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62 | |
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63 | void _Thread_Do_dispatch( Per_CPU_Control *cpu_self, ISR_Level level ) |
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64 | { |
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65 | Thread_Control *executing; |
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66 | |
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67 | _Assert( cpu_self->thread_dispatch_disable_level == 1 ); |
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68 | |
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69 | executing = cpu_self->executing; |
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70 | |
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71 | do { |
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72 | Thread_Control *heir = _Thread_Get_heir_and_make_it_executing( cpu_self ); |
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73 | |
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74 | /* |
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75 | * When the heir and executing are the same, then we are being |
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76 | * requested to do the post switch dispatching. This is normally |
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77 | * done to dispatch signals. |
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78 | */ |
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79 | if ( heir == executing ) |
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80 | goto post_switch; |
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81 | |
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82 | /* |
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83 | * Since heir and executing are not the same, we need to do a real |
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84 | * context switch. |
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85 | */ |
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86 | #if __RTEMS_ADA__ |
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87 | executing->rtems_ada_self = rtems_ada_self; |
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88 | rtems_ada_self = heir->rtems_ada_self; |
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89 | #endif |
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90 | if ( heir->budget_algorithm == THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE ) |
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91 | heir->cpu_time_budget = rtems_configuration_get_ticks_per_timeslice(); |
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92 | |
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93 | /* |
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94 | * On SMP the complete context switch must be atomic with respect to one |
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95 | * processor. See also _Thread_Handler() since _Context_switch() may branch |
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96 | * to this function. |
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97 | */ |
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98 | #if !defined( RTEMS_SMP ) |
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99 | _ISR_Enable( level ); |
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100 | #endif |
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101 | |
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102 | _Thread_Update_cpu_time_used( |
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103 | executing, |
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104 | &cpu_self->time_of_last_context_switch |
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105 | ); |
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106 | |
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107 | #if !defined(__DYNAMIC_REENT__) |
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108 | /* |
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109 | * Switch libc's task specific data. |
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110 | */ |
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111 | if ( _Thread_libc_reent ) { |
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112 | executing->libc_reent = *_Thread_libc_reent; |
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113 | *_Thread_libc_reent = heir->libc_reent; |
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114 | } |
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115 | #endif |
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116 | |
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117 | _User_extensions_Thread_switch( executing, heir ); |
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118 | _Thread_Save_fp( executing ); |
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119 | _Context_Switch( &executing->Registers, &heir->Registers ); |
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120 | _Thread_Restore_fp( executing ); |
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121 | |
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122 | /* |
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123 | * We have to obtain this value again after the context switch since the |
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124 | * heir thread may have migrated from another processor. Values from the |
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125 | * stack or non-volatile registers reflect the old execution environment. |
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126 | */ |
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127 | cpu_self = _Per_CPU_Get(); |
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128 | |
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129 | _Thread_Debug_set_real_processor( executing, cpu_self ); |
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130 | |
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131 | #if !defined( RTEMS_SMP ) |
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132 | _ISR_Disable( level ); |
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133 | #endif |
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134 | } while ( |
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135 | #if defined( RTEMS_SMP ) |
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136 | false |
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137 | #else |
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138 | cpu_self->dispatch_necessary |
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139 | #endif |
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140 | ); |
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141 | |
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142 | post_switch: |
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143 | _Assert( cpu_self->thread_dispatch_disable_level == 1 ); |
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144 | cpu_self->thread_dispatch_disable_level = 0; |
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145 | _Profiling_Thread_dispatch_enable( cpu_self, 0 ); |
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146 | |
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147 | _ISR_Enable_without_giant( level ); |
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148 | |
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149 | _Thread_Run_post_switch_actions( executing ); |
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150 | } |
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151 | |
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152 | void _Thread_Dispatch( void ) |
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153 | { |
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154 | ISR_Level level; |
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155 | Per_CPU_Control *cpu_self; |
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156 | |
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157 | _ISR_Disable_without_giant( level ); |
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158 | |
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159 | cpu_self = _Per_CPU_Get(); |
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160 | |
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161 | if ( cpu_self->dispatch_necessary ) { |
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162 | _Profiling_Thread_dispatch_disable( cpu_self, 0 ); |
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163 | cpu_self->thread_dispatch_disable_level = 1; |
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164 | _Thread_Do_dispatch( cpu_self, level ); |
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165 | } else { |
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166 | _ISR_Enable_without_giant( level ); |
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167 | } |
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168 | } |
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