1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Dispatch Thread |
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5 | * @ingroup ScoreThread |
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6 | */ |
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7 | |
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8 | /* |
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9 | * COPYRIGHT (c) 1989-2009. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | */ |
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16 | |
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17 | #if HAVE_CONFIG_H |
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18 | #include "config.h" |
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19 | #endif |
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20 | |
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21 | #include <rtems/system.h> |
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22 | #include <rtems/score/apiext.h> |
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23 | #include <rtems/score/context.h> |
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24 | #include <rtems/score/interr.h> |
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25 | #include <rtems/score/isr.h> |
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26 | #include <rtems/score/object.h> |
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27 | #include <rtems/score/priority.h> |
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28 | #include <rtems/score/states.h> |
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29 | #include <rtems/score/sysstate.h> |
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30 | #include <rtems/score/thread.h> |
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31 | #include <rtems/score/threadq.h> |
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32 | #include <rtems/score/userextimpl.h> |
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33 | #include <rtems/score/wkspace.h> |
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34 | |
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35 | #ifndef __RTEMS_USE_TICKS_FOR_STATISTICS__ |
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36 | #include <rtems/score/timestamp.h> |
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37 | #endif |
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38 | |
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39 | #if defined(RTEMS_SMP) |
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40 | #include <rtems/score/smp.h> |
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41 | #endif |
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42 | |
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43 | void _Thread_Dispatch( void ) |
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44 | { |
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45 | Thread_Control *executing; |
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46 | Thread_Control *heir; |
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47 | ISR_Level level; |
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48 | |
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49 | #if defined(RTEMS_SMP) |
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50 | /* |
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51 | * WARNING: The SMP sequence has severe defects regarding the real-time |
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52 | * performance. |
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53 | * |
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54 | * Consider the following scenario. We have three tasks L (lowest |
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55 | * priority), M (middle priority), and H (highest priority). Now let a |
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56 | * thread dispatch from M to L happen. An interrupt occurs in |
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57 | * _Thread_Dispatch() here: |
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58 | * |
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59 | * void _Thread_Dispatch( void ) |
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60 | * { |
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61 | * [...] |
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62 | * |
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63 | * post_switch: |
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64 | * |
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65 | * _ISR_Enable( level ); |
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66 | * |
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67 | * <-- INTERRUPT |
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68 | * <-- AFTER INTERRUPT |
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69 | * |
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70 | * _Thread_Unnest_dispatch(); |
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71 | * |
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72 | * _API_extensions_Run_post_switch(); |
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73 | * } |
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74 | * |
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75 | * The interrupt event makes task H ready. The interrupt code will see |
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76 | * _Thread_Dispatch_disable_level > 0 and thus doesn't perform a |
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77 | * _Thread_Dispatch(). Now we return to position "AFTER INTERRUPT". This |
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78 | * means task L executes now although task H is ready! Task H will execute |
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79 | * once someone calls _Thread_Dispatch(). |
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80 | */ |
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81 | _Thread_Disable_dispatch(); |
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82 | |
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83 | /* |
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84 | * If necessary, send dispatch request to other cores. |
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85 | */ |
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86 | _SMP_Request_other_cores_to_dispatch(); |
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87 | #endif |
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88 | |
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89 | /* |
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90 | * Now determine if we need to perform a dispatch on the current CPU. |
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91 | */ |
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92 | executing = _Thread_Executing; |
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93 | _ISR_Disable( level ); |
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94 | while ( _Thread_Dispatch_necessary == true ) { |
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95 | heir = _Thread_Heir; |
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96 | #ifndef RTEMS_SMP |
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97 | _Thread_Dispatch_set_disable_level( 1 ); |
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98 | #endif |
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99 | _Thread_Dispatch_necessary = false; |
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100 | _Thread_Executing = heir; |
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101 | |
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102 | /* |
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103 | * When the heir and executing are the same, then we are being |
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104 | * requested to do the post switch dispatching. This is normally |
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105 | * done to dispatch signals. |
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106 | */ |
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107 | if ( heir == executing ) |
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108 | goto post_switch; |
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109 | |
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110 | /* |
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111 | * Since heir and executing are not the same, we need to do a real |
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112 | * context switch. |
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113 | */ |
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114 | #if __RTEMS_ADA__ |
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115 | executing->rtems_ada_self = rtems_ada_self; |
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116 | rtems_ada_self = heir->rtems_ada_self; |
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117 | #endif |
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118 | if ( heir->budget_algorithm == THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE ) |
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119 | heir->cpu_time_budget = _Thread_Ticks_per_timeslice; |
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120 | |
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121 | _ISR_Enable( level ); |
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122 | |
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123 | #ifndef __RTEMS_USE_TICKS_FOR_STATISTICS__ |
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124 | { |
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125 | Timestamp_Control uptime, ran; |
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126 | _TOD_Get_uptime( &uptime ); |
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127 | _Timestamp_Subtract( |
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128 | &_Thread_Time_of_last_context_switch, |
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129 | &uptime, |
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130 | &ran |
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131 | ); |
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132 | _Timestamp_Add_to( &executing->cpu_time_used, &ran ); |
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133 | _Thread_Time_of_last_context_switch = uptime; |
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134 | } |
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135 | #else |
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136 | { |
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137 | _TOD_Get_uptime( &_Thread_Time_of_last_context_switch ); |
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138 | heir->cpu_time_used++; |
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139 | } |
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140 | #endif |
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141 | |
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142 | /* |
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143 | * Switch libc's task specific data. |
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144 | */ |
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145 | if ( _Thread_libc_reent ) { |
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146 | executing->libc_reent = *_Thread_libc_reent; |
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147 | *_Thread_libc_reent = heir->libc_reent; |
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148 | } |
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149 | |
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150 | _User_extensions_Thread_switch( executing, heir ); |
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151 | |
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152 | /* |
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153 | * If the CPU has hardware floating point, then we must address saving |
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154 | * and restoring it as part of the context switch. |
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155 | * |
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156 | * The second conditional compilation section selects the algorithm used |
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157 | * to context switch between floating point tasks. The deferred algorithm |
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158 | * can be significantly better in a system with few floating point tasks |
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159 | * because it reduces the total number of save and restore FP context |
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160 | * operations. However, this algorithm can not be used on all CPUs due |
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161 | * to unpredictable use of FP registers by some compilers for integer |
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162 | * operations. |
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163 | */ |
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164 | |
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165 | #if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) |
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166 | #if ( CPU_USE_DEFERRED_FP_SWITCH != TRUE ) |
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167 | if ( executing->fp_context != NULL ) |
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168 | _Context_Save_fp( &executing->fp_context ); |
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169 | #endif |
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170 | #endif |
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171 | |
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172 | _Context_Switch( &executing->Registers, &heir->Registers ); |
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173 | |
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174 | #if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) |
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175 | #if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE ) |
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176 | if ( (executing->fp_context != NULL) && |
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177 | !_Thread_Is_allocated_fp( executing ) ) { |
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178 | if ( _Thread_Allocated_fp != NULL ) |
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179 | _Context_Save_fp( &_Thread_Allocated_fp->fp_context ); |
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180 | _Context_Restore_fp( &executing->fp_context ); |
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181 | _Thread_Allocated_fp = executing; |
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182 | } |
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183 | #else |
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184 | if ( executing->fp_context != NULL ) |
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185 | _Context_Restore_fp( &executing->fp_context ); |
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186 | #endif |
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187 | #endif |
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188 | |
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189 | executing = _Thread_Executing; |
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190 | |
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191 | _ISR_Disable( level ); |
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192 | } |
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193 | |
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194 | post_switch: |
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195 | #ifndef RTEMS_SMP |
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196 | _Thread_Dispatch_set_disable_level( 0 ); |
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197 | #endif |
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198 | |
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199 | _ISR_Enable( level ); |
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200 | |
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201 | #ifdef RTEMS_SMP |
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202 | _Thread_Unnest_dispatch(); |
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203 | #endif |
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204 | |
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205 | _API_extensions_Run_post_switch( executing ); |
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206 | } |
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