[05df0a8] | 1 | /* |
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| 2 | * Thread Handler |
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| 3 | * |
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| 4 | * |
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[08311cc3] | 5 | * COPYRIGHT (c) 1989-1999. |
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[05df0a8] | 6 | * On-Line Applications Research Corporation (OAR). |
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| 7 | * |
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| 8 | * The license and distribution terms for this file may be |
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| 9 | * found in found in the file LICENSE in this distribution or at |
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[dd687d97] | 10 | * http://www.rtems.com/license/LICENSE. |
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[05df0a8] | 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | |
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[a8eed23] | 15 | #if HAVE_CONFIG_H |
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| 16 | #include "config.h" |
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| 17 | #endif |
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| 18 | |
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[05df0a8] | 19 | #include <rtems/system.h> |
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| 20 | #include <rtems/score/apiext.h> |
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| 21 | #include <rtems/score/context.h> |
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| 22 | #include <rtems/score/interr.h> |
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| 23 | #include <rtems/score/isr.h> |
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| 24 | #include <rtems/score/object.h> |
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| 25 | #include <rtems/score/priority.h> |
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| 26 | #include <rtems/score/states.h> |
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| 27 | #include <rtems/score/sysstate.h> |
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| 28 | #include <rtems/score/thread.h> |
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| 29 | #include <rtems/score/threadq.h> |
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| 30 | #include <rtems/score/userext.h> |
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| 31 | #include <rtems/score/wkspace.h> |
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| 32 | |
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| 33 | /*PAGE |
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| 34 | * |
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| 35 | * _Thread_Dispatch |
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| 36 | * |
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| 37 | * This kernel routine determines if a dispatch is needed, and if so |
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| 38 | * dispatches to the heir thread. Once the heir is running an attempt |
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| 39 | * is made to dispatch any ASRs. |
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| 40 | * |
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| 41 | * ALTERNATE ENTRY POINTS: |
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| 42 | * void _Thread_Enable_dispatch(); |
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| 43 | * |
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| 44 | * Input parameters: NONE |
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| 45 | * |
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| 46 | * Output parameters: NONE |
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| 47 | * |
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| 48 | * INTERRUPT LATENCY: |
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| 49 | * dispatch thread |
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| 50 | * no dispatch thread |
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| 51 | */ |
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| 52 | |
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| 53 | #if ( CPU_INLINE_ENABLE_DISPATCH == FALSE ) |
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| 54 | void _Thread_Enable_dispatch( void ) |
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| 55 | { |
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| 56 | if ( --_Thread_Dispatch_disable_level ) |
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| 57 | return; |
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| 58 | _Thread_Dispatch(); |
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| 59 | } |
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| 60 | #endif |
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| 61 | |
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| 62 | void _Thread_Dispatch( void ) |
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| 63 | { |
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| 64 | Thread_Control *executing; |
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| 65 | Thread_Control *heir; |
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| 66 | ISR_Level level; |
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| 67 | |
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| 68 | executing = _Thread_Executing; |
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| 69 | _ISR_Disable( level ); |
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| 70 | while ( _Context_Switch_necessary == TRUE ) { |
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| 71 | heir = _Thread_Heir; |
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| 72 | _Thread_Dispatch_disable_level = 1; |
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| 73 | _Context_Switch_necessary = FALSE; |
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| 74 | _Thread_Executing = heir; |
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| 75 | executing->rtems_ada_self = rtems_ada_self; |
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| 76 | rtems_ada_self = heir->rtems_ada_self; |
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[e9f6d10] | 77 | if ( heir->budget_algorithm == THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE ) |
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| 78 | heir->cpu_time_budget = _Thread_Ticks_per_timeslice; |
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[05df0a8] | 79 | _ISR_Enable( level ); |
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| 80 | |
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| 81 | heir->ticks_executed++; |
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| 82 | |
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[0df8293e] | 83 | /* |
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| 84 | * Switch libc's task specific data. |
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| 85 | */ |
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| 86 | if ( _Thread_libc_reent ) { |
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| 87 | executing->libc_reent = *_Thread_libc_reent; |
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| 88 | *_Thread_libc_reent = heir->libc_reent; |
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| 89 | } |
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| 90 | |
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[05df0a8] | 91 | _User_extensions_Thread_switch( executing, heir ); |
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| 92 | |
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| 93 | /* |
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| 94 | * If the CPU has hardware floating point, then we must address saving |
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| 95 | * and restoring it as part of the context switch. |
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| 96 | * |
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| 97 | * The second conditional compilation section selects the algorithm used |
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| 98 | * to context switch between floating point tasks. The deferred algorithm |
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| 99 | * can be significantly better in a system with few floating point tasks |
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| 100 | * because it reduces the total number of save and restore FP context |
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| 101 | * operations. However, this algorithm can not be used on all CPUs due |
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| 102 | * to unpredictable use of FP registers by some compilers for integer |
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| 103 | * operations. |
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| 104 | */ |
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| 105 | |
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[48f89683] | 106 | #if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) |
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| 107 | #if ( CPU_USE_DEFERRED_FP_SWITCH != TRUE ) |
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| 108 | if ( executing->fp_context != NULL ) |
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| 109 | _Context_Save_fp( &executing->fp_context ); |
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| 110 | #endif |
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| 111 | #endif |
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| 112 | |
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| 113 | _Context_Switch( &executing->Registers, &heir->Registers ); |
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| 114 | |
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[ca7858bb] | 115 | #if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE ) |
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[05df0a8] | 116 | #if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE ) |
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[63f786e] | 117 | if ( (executing->fp_context != NULL) && |
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| 118 | !_Thread_Is_allocated_fp( executing ) ) { |
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[05df0a8] | 119 | if ( _Thread_Allocated_fp != NULL ) |
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| 120 | _Context_Save_fp( &_Thread_Allocated_fp->fp_context ); |
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[48f89683] | 121 | _Context_Restore_fp( &executing->fp_context ); |
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| 122 | _Thread_Allocated_fp = executing; |
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[05df0a8] | 123 | } |
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| 124 | #else |
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| 125 | if ( executing->fp_context != NULL ) |
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[48f89683] | 126 | _Context_Restore_fp( &executing->fp_context ); |
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[05df0a8] | 127 | #endif |
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| 128 | #endif |
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| 129 | |
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| 130 | executing = _Thread_Executing; |
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| 131 | |
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| 132 | _ISR_Disable( level ); |
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| 133 | } |
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| 134 | |
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| 135 | _Thread_Dispatch_disable_level = 0; |
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| 136 | |
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| 137 | _ISR_Enable( level ); |
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| 138 | |
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| 139 | if ( _Thread_Do_post_task_switch_extension || |
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| 140 | executing->do_post_task_switch_extension ) { |
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| 141 | executing->do_post_task_switch_extension = FALSE; |
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| 142 | _API_extensions_Run_postswitch(); |
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| 143 | } |
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[05279b84] | 144 | |
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[05df0a8] | 145 | } |
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