4.115
Last change
on this file since 06dcaf0 was
06dcaf0,
checked in by Joel Sherrill <joel.sherrill@…>, on 03/16/11 at 20:05:06
|
2011-03-16 Jennifer Averett <jennifer.averett@…>
PR 1729/cpukit
- configure.ac, sapi/include/confdefs.h, sapi/src/exinit.c,
score/Makefile.am, score/preinstall.am,
score/cpu/i386/rtems/score/cpu.h, score/cpu/sparc/cpu_asm.S,
score/cpu/sparc/rtems/score/cpu.h,
score/include/rtems/score/basedefs.h,
score/include/rtems/score/context.h,
score/include/rtems/score/percpu.h, score/src/percpu.c,
score/src/thread.c, score/src/threadcreateidle.c: Add next step in
SMP support. This adds an allocated array of the Per_CPU structures
to support multiple cpus vs a single instance of the structure which
is still used if SMP support is disabled. Configuration support is
also added to explicitly enable or disable SMP. But SMP can only be
enabled for the CPUs which will support it initially -- SPARC and
i386. With the stub BSP support, a BSP can be run as a single core
SMP system from an RTEMS data structure standpoint.
- aclocal/check-smp.m4, aclocal/enable-smp.m4,
score/include/rtems/bspsmp.h, score/include/rtems/score/smplock.h,
score/src/smp.c, score/src/smplock.c: New files.
|
-
Property mode set to
100644
|
File size:
898 bytes
|
Line | |
---|
1 | /* |
---|
2 | * COPYRIGHT (c) 1989-2011. |
---|
3 | * On-Line Applications Research Corporation (OAR). |
---|
4 | * |
---|
5 | * The license and distribution terms for this file may be |
---|
6 | * found in the file LICENSE in this distribution or at |
---|
7 | * http://www.rtems.com/license/LICENSE. |
---|
8 | * |
---|
9 | * $Id$ |
---|
10 | */ |
---|
11 | |
---|
12 | #if HAVE_CONFIG_H |
---|
13 | #include "config.h" |
---|
14 | #endif |
---|
15 | |
---|
16 | #include <rtems/system.h> |
---|
17 | #include <rtems/score/smplock.h> |
---|
18 | |
---|
19 | void _SMP_lock_Spinlock_Initialize( |
---|
20 | SMP_lock_Control *lock |
---|
21 | ) |
---|
22 | { |
---|
23 | *lock = 0; |
---|
24 | } |
---|
25 | |
---|
26 | ISR_Level _SMP_lock_Spinlock_Obtain( |
---|
27 | SMP_lock_Control *lock |
---|
28 | ) |
---|
29 | { |
---|
30 | ISR_Level level; |
---|
31 | uint32_t value = 1; |
---|
32 | uint32_t previous; |
---|
33 | |
---|
34 | /* Note: Disable provides an implicit memory barrier. */ |
---|
35 | _ISR_Disable( level ); |
---|
36 | do { |
---|
37 | SMP_CPU_SWAP( lock, value, previous ); |
---|
38 | } while (previous == 1); |
---|
39 | return level; |
---|
40 | } |
---|
41 | |
---|
42 | void _SMP_lock_Spinlock_Release( |
---|
43 | SMP_lock_Control *lock, |
---|
44 | ISR_Level level |
---|
45 | ) |
---|
46 | { |
---|
47 | *lock = 0; |
---|
48 | _ISR_Enable( level ); |
---|
49 | } |
---|
Note: See
TracBrowser
for help on using the repository browser.