5
Last change
on this file since 271690e was
271690e,
checked in by Sebastian Huber <sebastian.huber@…>, on 10/11/16 at 12:42:55
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score: Enhance _SMP_barrier_Wait()
Indicate which processor released the barrier. Similar to
pthread_barrier_wait().
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-
Property mode set to
100644
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File size:
1.1 KB
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1 | /* |
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2 | * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #if HAVE_CONFIG_H |
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16 | #include "config.h" |
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17 | #endif |
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18 | |
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19 | #include <rtems/score/smpbarrier.h> |
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20 | |
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21 | bool _SMP_barrier_Wait( |
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22 | SMP_barrier_Control *control, |
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23 | SMP_barrier_State *state, |
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24 | unsigned int count |
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25 | ) |
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26 | { |
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27 | unsigned int sense = ~state->sense; |
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28 | unsigned int previous_value; |
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29 | bool performed_release; |
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30 | |
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31 | state->sense = sense; |
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32 | |
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33 | previous_value = _Atomic_Fetch_add_uint( |
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34 | &control->value, |
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35 | 1U, |
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36 | ATOMIC_ORDER_RELAXED |
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37 | ); |
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38 | |
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39 | if ( previous_value + 1U == count ) { |
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40 | _Atomic_Store_uint( &control->value, 0U, ATOMIC_ORDER_RELAXED ); |
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41 | _Atomic_Store_uint( &control->sense, sense, ATOMIC_ORDER_RELEASE ); |
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42 | performed_release = true; |
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43 | } else { |
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44 | while ( |
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45 | _Atomic_Load_uint( &control->sense, ATOMIC_ORDER_ACQUIRE ) != sense |
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46 | ) { |
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47 | /* Wait */ |
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48 | } |
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49 | |
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50 | performed_release = false; |
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51 | } |
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52 | |
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53 | return performed_release; |
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54 | } |
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