1 | /* |
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2 | * COPYRIGHT (c) 1989-2011. |
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3 | * On-Line Applications Research Corporation (OAR). |
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4 | * |
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5 | * The license and distribution terms for this file may be |
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6 | * found in the file LICENSE in this distribution or at |
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7 | * http://www.rtems.com/license/LICENSE. |
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8 | * |
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9 | * $Id$ |
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10 | */ |
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11 | |
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12 | #if HAVE_CONFIG_H |
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13 | #include "config.h" |
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14 | #endif |
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15 | |
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16 | #include <rtems/system.h> |
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17 | #include <rtems/bspsmp.h> |
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18 | #include <rtems/score/smp.h> |
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19 | #include <rtems/score/thread.h> |
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20 | |
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21 | #if defined(RTEMS_SMP) |
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22 | #define SMP_DEBUG |
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23 | |
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24 | #if defined(SMP_DEBUG) |
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25 | #include <rtems/bspIo.h> |
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26 | #endif |
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27 | |
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28 | void rtems_smp_run_first_task(int cpu) |
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29 | { |
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30 | Thread_Control *heir; |
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31 | |
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32 | /* |
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33 | * This CPU has an heir thread so we need to dispatch it. |
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34 | */ |
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35 | heir = _Thread_Heir; |
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36 | |
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37 | /* |
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38 | * This is definitely a hack until we have SMP scheduling. Since there |
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39 | * is only one executing and heir right now, we have to fake this out. |
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40 | */ |
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41 | _Thread_Dispatch_set_disable_level(1); |
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42 | _Thread_Executing = heir; |
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43 | _CPU_Context_switch_to_first_task_smp( &heir->Registers ); |
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44 | } |
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45 | |
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46 | void rtems_smp_secondary_cpu_initialize(void) |
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47 | { |
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48 | int cpu; |
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49 | |
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50 | cpu = bsp_smp_processor_id(); |
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51 | |
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52 | bsp_smp_secondary_cpu_initialize(cpu); |
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53 | |
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54 | #if defined(SMP_DEBUG) |
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55 | printk( "Made it to %d -- ", cpu ); |
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56 | #endif |
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57 | |
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58 | /* |
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59 | * Inform the primary CPU that this secondary CPU is initialized |
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60 | * and ready to dispatch to the first thread it is supposed to |
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61 | * execute when the primary CPU is ready. |
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62 | */ |
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63 | _Per_CPU_Information[cpu].state = RTEMS_BSP_SMP_CPU_INITIALIZED; |
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64 | |
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65 | /* |
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66 | * HACK: Should not have to enable interrupts in real system here. |
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67 | * It should happen as part of switching to the first task. |
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68 | */ |
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69 | |
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70 | _Per_CPU_Information[cpu].isr_nest_level = 1; |
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71 | _ISR_Set_level( 0 ); |
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72 | while(1) ; |
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73 | } |
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74 | |
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75 | void rtems_smp_process_interrupt(void) |
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76 | { |
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77 | int cpu; |
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78 | uint32_t message; |
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79 | ISR_Level level; |
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80 | |
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81 | cpu = bsp_smp_processor_id(); |
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82 | |
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83 | level = _SMP_lock_spinlock_simple_Obtain( &_Per_CPU_Information[cpu].lock ); |
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84 | message = _Per_CPU_Information[cpu].message; |
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85 | _Per_CPU_Information[cpu].message &= ~message; |
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86 | _SMP_lock_spinlock_simple_Release( &_Per_CPU_Information[cpu].lock, level ); |
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87 | |
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88 | #if defined(SMP_DEBUG) |
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89 | { |
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90 | void *sp = __builtin_frame_address(0); |
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91 | if ( !(message & RTEMS_BSP_SMP_SHUTDOWN) ) |
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92 | printk( "ISR on CPU %d -- (0x%02x) (0x%p)\n", cpu, message, sp ); |
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93 | printk( "Dispatch level %d\n", _Thread_Dispatch_disable_level ); |
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94 | } |
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95 | #endif |
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96 | |
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97 | if ( message & RTEMS_BSP_SMP_FIRST_TASK ) { |
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98 | _Per_CPU_Information[cpu].isr_nest_level = 0; |
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99 | _Per_CPU_Information[cpu].message = 0; |
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100 | _Per_CPU_Information[cpu].state = RTEMS_BSP_SMP_CPU_INITIALIZED; |
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101 | rtems_smp_run_first_task(cpu); |
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102 | /* does not return */ |
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103 | } |
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104 | |
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105 | if ( message & RTEMS_BSP_SMP_SHUTDOWN ) { |
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106 | ISR_Level level; |
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107 | _Thread_Dispatch_set_disable_level(0); |
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108 | _Per_CPU_Information[cpu].isr_nest_level = 0; |
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109 | _Per_CPU_Information[cpu].state = RTEMS_BSP_SMP_CPU_SHUTDOWN; |
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110 | _ISR_Disable( level ); |
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111 | while(1) |
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112 | ; |
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113 | /* does not continue past here */ |
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114 | } |
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115 | |
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116 | if ( message & RTEMS_BSP_SMP_CONTEXT_SWITCH_NECESSARY ) { |
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117 | printk( "switch needed\n" ); |
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118 | _Per_CPU_Information[cpu].dispatch_necessary = true; |
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119 | } |
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120 | } |
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121 | |
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122 | void rtems_smp_send_message( |
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123 | int cpu, |
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124 | uint32_t message |
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125 | ) |
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126 | { |
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127 | ISR_Level level; |
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128 | |
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129 | level = _SMP_lock_spinlock_simple_Obtain( &_Per_CPU_Information[cpu].lock ); |
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130 | _Per_CPU_Information[cpu].message |= message; |
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131 | _SMP_lock_spinlock_simple_Release( &_Per_CPU_Information[cpu].lock, level ); |
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132 | bsp_smp_interrupt_cpu( cpu ); |
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133 | } |
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134 | |
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135 | void rtems_smp_broadcast_message( |
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136 | uint32_t message |
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137 | ) |
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138 | { |
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139 | int dest_cpu; |
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140 | int cpu; |
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141 | ISR_Level level; |
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142 | |
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143 | cpu = bsp_smp_processor_id(); |
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144 | |
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145 | for ( dest_cpu=0 ; dest_cpu < _SMP_Processor_count; dest_cpu++ ) { |
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146 | if ( cpu == dest_cpu ) |
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147 | continue; |
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148 | level = _SMP_lock_spinlock_simple_Obtain( &_Per_CPU_Information[cpu].lock ); |
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149 | _Per_CPU_Information[dest_cpu].message |= message; |
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150 | _SMP_lock_spinlock_simple_Release( &_Per_CPU_Information[cpu].lock, level ); |
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151 | } |
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152 | bsp_smp_broadcast_interrupt(); |
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153 | } |
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154 | #endif |
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