source: rtems/cpukit/score/src/percpuasm.c @ c6c998b

4.115
Last change on this file since c6c998b was d19cce29, checked in by Sebastian Huber <sebastian.huber@…>, on 08/05/13 at 12:54:11

score: Per-CPU thread dispatch disable level

Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.

The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().

The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).

As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().

A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.

All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
  • Property mode set to 100644
File size: 1.8 KB
Line 
1/*
2 * Copyright (c) 2012 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Obere Lagerstr. 30
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#if HAVE_CONFIG_H
16  #include "config.h"
17#endif
18
19#include <rtems/score/cpu.h>
20
21#define _RTEMS_PERCPU_DEFINE_OFFSETS
22#include <rtems/score/percpu.h>
23
24RTEMS_STATIC_ASSERT(
25  sizeof(void *) == CPU_SIZEOF_POINTER,
26  CPU_SIZEOF_POINTER
27);
28
29#if defined( __SIZEOF_POINTER__ )
30  RTEMS_STATIC_ASSERT(
31    CPU_SIZEOF_POINTER == __SIZEOF_POINTER__,
32    __SIZEOF_POINTER__
33  );
34#endif
35
36RTEMS_STATIC_ASSERT(
37  sizeof( CPU_Per_CPU_control ) == CPU_PER_CPU_CONTROL_SIZE,
38  CPU_PER_CPU_CONTROL_SIZE
39);
40
41#if defined( RTEMS_SMP )
42  RTEMS_STATIC_ASSERT(
43    sizeof( Per_CPU_Control_envelope ) == PER_CPU_CONTROL_SIZE,
44    PER_CPU_CONTROL_SIZE
45  );
46#endif
47
48RTEMS_STATIC_ASSERT(
49  offsetof(Per_CPU_Control, isr_nest_level) == PER_CPU_ISR_NEST_LEVEL,
50  PER_CPU_ISR_NEST_LEVEL
51);
52
53RTEMS_STATIC_ASSERT(
54  offsetof(Per_CPU_Control, thread_dispatch_disable_level)
55    == PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL,
56  PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL
57);
58
59RTEMS_STATIC_ASSERT(
60  offsetof(Per_CPU_Control, dispatch_necessary) == PER_CPU_DISPATCH_NEEDED,
61  PER_CPU_DISPATCH_NEEDED
62);
63
64#if CPU_ALLOCATE_INTERRUPT_STACK == TRUE \
65  || CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE
66  RTEMS_STATIC_ASSERT(
67    offsetof(Per_CPU_Control, interrupt_stack_low)
68      == PER_CPU_INTERRUPT_STACK_LOW,
69    PER_CPU_INTERRUPT_STACK_LOW
70  );
71
72  RTEMS_STATIC_ASSERT(
73    offsetof(Per_CPU_Control, interrupt_stack_high)
74      == PER_CPU_INTERRUPT_STACK_HIGH,
75    PER_CPU_INTERRUPT_STACK_HIGH
76  );
77#endif
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