1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @ingroup RTEMSScorePerCPU |
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7 | * |
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8 | * @brief This source file contains the static assertions for defines used in |
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9 | * assembler files. |
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10 | */ |
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11 | |
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12 | /* |
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13 | * Copyright (c) 2012, 2016 embedded brains GmbH. All rights reserved. |
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14 | * |
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15 | * embedded brains GmbH |
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16 | * Dornierstr. 4 |
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17 | * 82178 Puchheim |
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18 | * Germany |
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19 | * <rtems@embedded-brains.de> |
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20 | * |
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21 | * Redistribution and use in source and binary forms, with or without |
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22 | * modification, are permitted provided that the following conditions |
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23 | * are met: |
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24 | * 1. Redistributions of source code must retain the above copyright |
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25 | * notice, this list of conditions and the following disclaimer. |
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26 | * 2. Redistributions in binary form must reproduce the above copyright |
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27 | * notice, this list of conditions and the following disclaimer in the |
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28 | * documentation and/or other materials provided with the distribution. |
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29 | * |
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30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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31 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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33 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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34 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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35 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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36 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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37 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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38 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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39 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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40 | * POSSIBILITY OF SUCH DAMAGE. |
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41 | */ |
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42 | |
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43 | #ifdef HAVE_CONFIG_H |
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44 | #include "config.h" |
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45 | #endif |
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46 | |
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47 | #include <rtems/score/cpu.h> |
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48 | |
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49 | #define _RTEMS_PERCPU_DEFINE_OFFSETS |
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50 | #include <rtems/score/percpu.h> |
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51 | |
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52 | #define PER_CPU_IS_POWER_OF_TWO( value ) \ |
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53 | ( ( ( ( value ) - 1 ) & ( value ) ) == 0 ) |
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54 | |
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55 | /* |
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56 | * The minimum alignment of two is due to the Heap Handler which uses the |
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57 | * HEAP_PREV_BLOCK_USED flag to indicate that the previous block is used. |
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58 | */ |
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59 | |
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60 | RTEMS_STATIC_ASSERT( |
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61 | CPU_ALIGNMENT >= 2 && PER_CPU_IS_POWER_OF_TWO( CPU_ALIGNMENT ), |
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62 | CPU_ALIGNMENT |
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63 | ); |
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64 | |
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65 | RTEMS_STATIC_ASSERT( |
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66 | CPU_HEAP_ALIGNMENT >= 2 && PER_CPU_IS_POWER_OF_TWO( CPU_HEAP_ALIGNMENT ), |
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67 | CPU_HEAP_ALIGNMENT_0 |
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68 | ); |
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69 | |
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70 | RTEMS_STATIC_ASSERT( |
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71 | CPU_HEAP_ALIGNMENT >= CPU_ALIGNMENT, |
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72 | CPU_HEAP_ALIGNMENT_1 |
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73 | ); |
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74 | |
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75 | RTEMS_STATIC_ASSERT( |
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76 | CPU_STACK_ALIGNMENT >= CPU_HEAP_ALIGNMENT && |
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77 | PER_CPU_IS_POWER_OF_TWO( CPU_STACK_ALIGNMENT ), |
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78 | CPU_STACK_ALIGNMENT |
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79 | ); |
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80 | |
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81 | RTEMS_STATIC_ASSERT( |
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82 | sizeof(void *) == CPU_SIZEOF_POINTER, |
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83 | CPU_SIZEOF_POINTER |
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84 | ); |
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85 | |
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86 | #if defined( __SIZEOF_POINTER__ ) |
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87 | RTEMS_STATIC_ASSERT( |
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88 | CPU_SIZEOF_POINTER == __SIZEOF_POINTER__, |
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89 | __SIZEOF_POINTER__ |
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90 | ); |
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91 | #endif |
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92 | |
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93 | #if CPU_PER_CPU_CONTROL_SIZE > 0 |
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94 | RTEMS_STATIC_ASSERT( |
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95 | sizeof( CPU_Per_CPU_control ) == CPU_PER_CPU_CONTROL_SIZE, |
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96 | CPU_PER_CPU_CONTROL_SIZE |
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97 | ); |
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98 | #endif |
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99 | |
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100 | #if defined( RTEMS_SMP ) |
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101 | RTEMS_STATIC_ASSERT( |
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102 | sizeof( Per_CPU_Control_envelope ) == PER_CPU_CONTROL_SIZE, |
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103 | PER_CPU_CONTROL_SIZE |
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104 | ); |
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105 | #endif |
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106 | |
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107 | RTEMS_STATIC_ASSERT( |
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108 | offsetof(Per_CPU_Control, isr_nest_level) == PER_CPU_ISR_NEST_LEVEL, |
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109 | PER_CPU_ISR_NEST_LEVEL |
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110 | ); |
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111 | |
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112 | RTEMS_STATIC_ASSERT( |
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113 | offsetof(Per_CPU_Control, isr_dispatch_disable) |
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114 | == PER_CPU_ISR_DISPATCH_DISABLE, |
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115 | PER_CPU_ISR_DISPATCH_DISABLE |
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116 | ); |
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117 | |
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118 | RTEMS_STATIC_ASSERT( |
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119 | offsetof(Per_CPU_Control, thread_dispatch_disable_level) |
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120 | == PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL, |
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121 | PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL |
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122 | ); |
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123 | |
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124 | RTEMS_STATIC_ASSERT( |
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125 | offsetof(Per_CPU_Control, executing) == PER_CPU_OFFSET_EXECUTING, |
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126 | PER_CPU_OFFSET_EXECUTING |
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127 | ); |
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128 | |
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129 | RTEMS_STATIC_ASSERT( |
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130 | offsetof(Per_CPU_Control, heir) == PER_CPU_OFFSET_HEIR, |
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131 | PER_CPU_OFFSET_HEIR |
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132 | ); |
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133 | |
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134 | RTEMS_STATIC_ASSERT( |
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135 | offsetof(Per_CPU_Control, dispatch_necessary) == PER_CPU_DISPATCH_NEEDED, |
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136 | PER_CPU_DISPATCH_NEEDED |
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137 | ); |
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138 | |
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139 | #if defined(RTEMS_SMP) |
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140 | RTEMS_STATIC_ASSERT( |
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141 | offsetof(Per_CPU_Control, Interrupt_frame) == PER_CPU_INTERRUPT_FRAME_AREA, |
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142 | PER_CPU_INTERRUPT_FRAME_AREA |
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143 | ); |
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144 | |
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145 | RTEMS_STATIC_ASSERT( |
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146 | sizeof( CPU_Interrupt_frame ) == CPU_INTERRUPT_FRAME_SIZE, |
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147 | CPU_INTERRUPT_FRAME_SIZE |
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148 | ); |
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149 | #endif |
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150 | |
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151 | RTEMS_STATIC_ASSERT( |
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152 | offsetof(Per_CPU_Control, interrupt_stack_low) |
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153 | == PER_CPU_INTERRUPT_STACK_LOW, |
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154 | PER_CPU_INTERRUPT_STACK_LOW |
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155 | ); |
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156 | |
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157 | RTEMS_STATIC_ASSERT( |
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158 | offsetof(Per_CPU_Control, interrupt_stack_high) |
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159 | == PER_CPU_INTERRUPT_STACK_HIGH, |
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160 | PER_CPU_INTERRUPT_STACK_HIGH |
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161 | ); |
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