source: rtems/cpukit/score/src/isrsmp.c @ 4f5baff

4.115
Last change on this file since 4f5baff was e655f7e, checked in by Alex Ivanov <alexivanov97@…>, on 11/29/12 at 18:39:19

score misc: Score misc: Clean up Doxygen #5

  • Property mode set to 100644
File size: 1.8 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief Initialize, Disable, Enable, Flash, Enter, Exit ISR Implementation
5 *  @ingroup ScoreISR
6 */
7
8/*
9 *  COPYRIGHT (c) 1989-2011.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 */
16
17#if HAVE_CONFIG_H
18#include "config.h"
19#endif
20
21#include <rtems/system.h>
22#include <rtems/score/isr.h>
23#include <rtems/score/thread.h>
24#include <rtems/score/smp.h>
25
26void _ISR_SMP_Initialize(void)
27{
28}
29
30ISR_Level _ISR_SMP_Disable(void)
31{
32  ISR_Level level;
33
34  _ISR_Disable_on_this_core( level );
35  return level;
36}
37
38void _ISR_SMP_Enable(ISR_Level level)
39{
40  _ISR_Enable_on_this_core( level );
41}
42
43void _ISR_SMP_Flash(ISR_Level level)
44{
45  ISR_Level ignored;
46
47  _ISR_SMP_Enable( level );
48  ignored = _ISR_SMP_Disable();
49}
50
51int _ISR_SMP_Enter(void)
52{
53  uint32_t isr_nest_level;
54  ISR_Level level;
55
56  _ISR_Disable_on_this_core( level );
57
58  isr_nest_level = _ISR_Nest_level++;
59
60  _Thread_Disable_dispatch();
61
62  return isr_nest_level;
63}
64
65int _ISR_SMP_Exit(void)
66{
67  ISR_Level level;
68  int       retval;
69
70  retval = 0;
71
72  _ISR_Disable_on_this_core( level );
73
74  _ISR_Nest_level--;
75
76  if ( _ISR_Nest_level == 0 ) {
77    if ( _Thread_Dispatch_necessary ) {
78      if ( _Thread_Dispatch_get_disable_level() == 1 ) {
79        retval = 1;
80      }
81    }
82  }
83
84  /*
85   *  SPARC has special support to avoid some nasty recursive type behaviour.
86   *  When dispatching in a thread and we want to return to it then it needs
87   *  to finish.
88   */
89  #if defined(__sparc__)
90    if ( _CPU_ISR_Dispatch_disable )
91      retval = 0;
92  #endif
93
94  _ISR_Enable_on_this_core( level );
95
96  _Thread_Dispatch_decrement_disable_level();
97
98   if ( retval == 0 )
99    _SMP_Request_other_cores_to_dispatch();
100
101  return retval;
102}
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