[e655f7e] | 1 | /** |
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| 2 | * @file |
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[dad36c52] | 3 | * |
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[e655f7e] | 4 | * @brief Initialize, Disable, Enable, Flash, Enter, Exit ISR Implementation |
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| 5 | * @ingroup ScoreISR |
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| 6 | */ |
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| 7 | |
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| 8 | /* |
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[dad36c52] | 9 | * COPYRIGHT (c) 1989-2011. |
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| 10 | * On-Line Applications Research Corporation (OAR). |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.rtems.com/license/LICENSE. |
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| 15 | */ |
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| 16 | |
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| 17 | #if HAVE_CONFIG_H |
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| 18 | #include "config.h" |
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| 19 | #endif |
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| 20 | |
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| 21 | #include <rtems/system.h> |
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| 22 | #include <rtems/score/isr.h> |
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| 23 | #include <rtems/score/thread.h> |
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[4fc370e] | 24 | #include <rtems/score/threaddispatch.h> |
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[dad36c52] | 25 | #include <rtems/score/smp.h> |
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| 26 | |
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| 27 | void _ISR_SMP_Initialize(void) |
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| 28 | { |
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| 29 | } |
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| 30 | |
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| 31 | ISR_Level _ISR_SMP_Disable(void) |
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| 32 | { |
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| 33 | ISR_Level level; |
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| 34 | |
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| 35 | _ISR_Disable_on_this_core( level ); |
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| 36 | return level; |
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| 37 | } |
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| 38 | |
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| 39 | void _ISR_SMP_Enable(ISR_Level level) |
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| 40 | { |
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| 41 | _ISR_Enable_on_this_core( level ); |
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| 42 | } |
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| 43 | |
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| 44 | void _ISR_SMP_Flash(ISR_Level level) |
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| 45 | { |
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| 46 | ISR_Level ignored; |
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| 47 | |
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| 48 | _ISR_SMP_Enable( level ); |
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| 49 | ignored = _ISR_SMP_Disable(); |
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| 50 | } |
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| 51 | |
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| 52 | int _ISR_SMP_Enter(void) |
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| 53 | { |
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| 54 | uint32_t isr_nest_level; |
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| 55 | ISR_Level level; |
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| 56 | |
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| 57 | _ISR_Disable_on_this_core( level ); |
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| 58 | |
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| 59 | isr_nest_level = _ISR_Nest_level++; |
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| 60 | |
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| 61 | _Thread_Disable_dispatch(); |
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| 62 | |
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| 63 | return isr_nest_level; |
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| 64 | } |
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| 65 | |
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| 66 | int _ISR_SMP_Exit(void) |
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| 67 | { |
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| 68 | ISR_Level level; |
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| 69 | int retval; |
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| 70 | |
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| 71 | retval = 0; |
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| 72 | |
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| 73 | _ISR_Disable_on_this_core( level ); |
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| 74 | |
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| 75 | _ISR_Nest_level--; |
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| 76 | |
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| 77 | if ( _ISR_Nest_level == 0 ) { |
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| 78 | if ( _Thread_Dispatch_necessary ) { |
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| 79 | if ( _Thread_Dispatch_get_disable_level() == 1 ) { |
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| 80 | retval = 1; |
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| 81 | } |
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| 82 | } |
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| 83 | } |
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| 84 | |
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| 85 | /* |
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| 86 | * SPARC has special support to avoid some nasty recursive type behaviour. |
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| 87 | * When dispatching in a thread and we want to return to it then it needs |
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| 88 | * to finish. |
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| 89 | */ |
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| 90 | #if defined(__sparc__) |
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| 91 | if ( _CPU_ISR_Dispatch_disable ) |
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| 92 | retval = 0; |
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| 93 | #endif |
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| 94 | |
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| 95 | _ISR_Enable_on_this_core( level ); |
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| 96 | |
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| 97 | _Thread_Dispatch_decrement_disable_level(); |
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| 98 | |
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| 99 | if ( retval == 0 ) |
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| 100 | _SMP_Request_other_cores_to_dispatch(); |
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| 101 | |
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| 102 | return retval; |
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| 103 | } |
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