1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup ScoreSMPBarrier |
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5 | * |
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6 | * @brief SMP Barrier API |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef _RTEMS_SCORE_SMPBARRIER_H |
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24 | #define _RTEMS_SCORE_SMPBARRIER_H |
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25 | |
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26 | #include <rtems/score/cpuopts.h> |
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27 | #include <rtems/score/atomic.h> |
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28 | |
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29 | #ifdef __cplusplus |
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30 | extern "C" { |
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31 | #endif /* __cplusplus */ |
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32 | |
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33 | /** |
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34 | * @defgroup ScoreSMPBarrier SMP Barriers |
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35 | * |
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36 | * @ingroup Score |
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37 | * |
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38 | * @brief The SMP barrier provides barrier synchronization for SMP systems at |
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39 | * the lowest level. |
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40 | * |
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41 | * The SMP barrier is implemented as a sense barrier, see also Herlihy and |
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42 | * Shavit, "The Art of Multiprocessor Programming", 17.3 Sense-Reversing |
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43 | * Barrier. |
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44 | * |
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45 | * @{ |
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46 | */ |
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47 | |
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48 | /** |
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49 | * @brief SMP barrier control. |
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50 | */ |
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51 | typedef struct { |
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52 | Atomic_Uint value; |
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53 | Atomic_Uint sense; |
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54 | } SMP_barrier_Control; |
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55 | |
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56 | /** |
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57 | * @brief SMP barrier per-thread state. |
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58 | * |
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59 | * Each user of the barrier must provide this per-thread state. |
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60 | */ |
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61 | typedef struct { |
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62 | unsigned int sense; |
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63 | } SMP_barrier_State; |
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64 | |
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65 | /** |
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66 | * @brief SMP barrier control initializer for static initialization. |
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67 | */ |
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68 | #define SMP_BARRIER_CONTROL_INITIALIZER \ |
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69 | { ATOMIC_INITIALIZER_UINT( 0U ), ATOMIC_INITIALIZER_UINT( 0U ) } |
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70 | |
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71 | /** |
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72 | * @brief SMP barrier per-thread state initializer for static initialization. |
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73 | */ |
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74 | #define SMP_BARRIER_STATE_INITIALIZER { 0U } |
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75 | |
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76 | /** |
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77 | * @brief Initializes a SMP barrier control. |
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78 | * |
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79 | * Concurrent initialization leads to unpredictable results. |
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80 | * |
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81 | * @param[out] control The SMP barrier control. |
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82 | */ |
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83 | static inline void _SMP_barrier_Control_initialize( |
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84 | SMP_barrier_Control *control |
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85 | ) |
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86 | { |
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87 | _Atomic_Init_uint( &control->value, 0U ); |
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88 | _Atomic_Init_uint( &control->sense, 0U ); |
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89 | } |
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90 | |
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91 | /** |
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92 | * @brief Initializes a SMP barrier per-thread state. |
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93 | * |
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94 | * @param[out] state The SMP barrier control. |
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95 | */ |
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96 | static inline void _SMP_barrier_State_initialize( |
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97 | SMP_barrier_State *state |
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98 | ) |
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99 | { |
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100 | state->sense = 0U; |
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101 | } |
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102 | |
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103 | /** |
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104 | * @brief Waits on the SMP barrier until count threads rendezvoused. |
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105 | * |
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106 | * @param[in, out] control The SMP barrier control. |
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107 | * @param[in, out] state The SMP barrier per-thread state. |
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108 | * @param[in] count The thread count bound to rendezvous. |
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109 | * |
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110 | * @retval true This processor performed the barrier release. |
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111 | * @retval false Otherwise. |
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112 | */ |
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113 | bool _SMP_barrier_Wait( |
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114 | SMP_barrier_Control *control, |
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115 | SMP_barrier_State *state, |
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116 | unsigned int count |
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117 | ); |
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118 | |
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119 | /**@}*/ |
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120 | |
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121 | #ifdef __cplusplus |
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122 | } |
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123 | #endif /* __cplusplus */ |
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124 | |
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125 | #endif /* _RTEMS_SCORE_SMPBARRIER_H */ |
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