source: rtems/cpukit/score/include/rtems/score/smpbarrier.h @ 271690e

5
Last change on this file since 271690e was 271690e, checked in by Sebastian Huber <sebastian.huber@…>, on 10/11/16 at 12:42:55

score: Enhance _SMP_barrier_Wait()

Indicate which processor released the barrier. Similar to
pthread_barrier_wait().

  • Property mode set to 100644
File size: 2.6 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup ScoreSMPBarrier
5 *
6 * @brief SMP Barrier API
7 */
8
9/*
10 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef _RTEMS_SCORE_SMPBARRIER_H
24#define _RTEMS_SCORE_SMPBARRIER_H
25
26#include <rtems/score/cpuopts.h>
27#include <rtems/score/atomic.h>
28
29#ifdef __cplusplus
30extern "C" {
31#endif /* __cplusplus */
32
33/**
34 * @defgroup ScoreSMPBarrier SMP Barriers
35 *
36 * @ingroup Score
37 *
38 * @brief The SMP barrier provides barrier synchronization for SMP systems at
39 * the lowest level.
40 *
41 * The SMP barrier is implemented as a sense barrier, see also Herlihy and
42 * Shavit, "The Art of Multiprocessor Programming", 17.3 Sense-Reversing
43 * Barrier.
44 *
45 * @{
46 */
47
48/**
49 * @brief SMP barrier control.
50 */
51typedef struct {
52  Atomic_Uint value;
53  Atomic_Uint sense;
54} SMP_barrier_Control;
55
56/**
57 * @brief SMP barrier per-thread state.
58 *
59 * Each user of the barrier must provide this per-thread state.
60 */
61typedef struct {
62  unsigned int sense;
63} SMP_barrier_State;
64
65/**
66 * @brief SMP barrier control initializer for static initialization.
67 */
68#define SMP_BARRIER_CONTROL_INITIALIZER \
69  { ATOMIC_INITIALIZER_UINT( 0U ), ATOMIC_INITIALIZER_UINT( 0U ) }
70
71/**
72 * @brief SMP barrier per-thread state initializer for static initialization.
73 */
74#define SMP_BARRIER_STATE_INITIALIZER { 0U }
75
76/**
77 * @brief Initializes a SMP barrier control.
78 *
79 * Concurrent initialization leads to unpredictable results.
80 *
81 * @param[out] control The SMP barrier control.
82 */
83static inline void _SMP_barrier_Control_initialize(
84  SMP_barrier_Control *control
85)
86{
87  _Atomic_Init_uint( &control->value, 0U );
88  _Atomic_Init_uint( &control->sense, 0U );
89}
90
91/**
92 * @brief Initializes a SMP barrier per-thread state.
93 *
94 * @param[out] state The SMP barrier control.
95 */
96static inline void _SMP_barrier_State_initialize(
97  SMP_barrier_State *state
98)
99{
100  state->sense = 0U;
101}
102
103/**
104 * @brief Waits on the SMP barrier until count threads rendezvoused.
105 *
106 * @param[in, out] control The SMP barrier control.
107 * @param[in, out] state The SMP barrier per-thread state.
108 * @param[in] count The thread count bound to rendezvous.
109 *
110 * @retval true This processor performed the barrier release.
111 * @retval false Otherwise.
112 */
113bool _SMP_barrier_Wait(
114  SMP_barrier_Control *control,
115  SMP_barrier_State *state,
116  unsigned int count
117);
118
119/**@}*/
120
121#ifdef __cplusplus
122}
123#endif /* __cplusplus */
124
125#endif /* _RTEMS_SCORE_SMPBARRIER_H */
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