1 | /** |
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2 | * @file rtems/score/percpu.h |
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3 | * |
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4 | * This include file defines the per CPU information required |
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5 | * by RTEMS. |
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6 | */ |
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7 | |
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8 | /* |
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9 | * COPYRIGHT (c) 1989-2011. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | */ |
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16 | |
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17 | #ifndef _RTEMS_PERCPU_H |
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18 | #define _RTEMS_PERCPU_H |
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19 | |
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20 | #include <rtems/score/cpu.h> |
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21 | |
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22 | #if defined( ASM ) |
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23 | #include <rtems/asm.h> |
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24 | #else |
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25 | #include <rtems/score/assert.h> |
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26 | #include <rtems/score/isrlock.h> |
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27 | #include <rtems/score/timestamp.h> |
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28 | #include <rtems/score/smp.h> |
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29 | #endif |
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30 | |
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31 | #ifdef __cplusplus |
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32 | extern "C" { |
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33 | #endif |
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34 | |
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35 | #if defined( RTEMS_SMP ) |
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36 | /* |
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37 | * This ensures that on SMP configurations the individual per-CPU controls |
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38 | * are on different cache lines to prevent false sharing. This define can be |
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39 | * used in assembler code to easily get the per-CPU control for a particular |
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40 | * processor. |
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41 | */ |
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42 | #define PER_CPU_CONTROL_SIZE_LOG2 7 |
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43 | |
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44 | #define PER_CPU_CONTROL_SIZE ( 1 << PER_CPU_CONTROL_SIZE_LOG2 ) |
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45 | #endif |
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46 | |
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47 | #if !defined( ASM ) |
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48 | |
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49 | #ifndef __THREAD_CONTROL_DEFINED__ |
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50 | #define __THREAD_CONTROL_DEFINED__ |
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51 | typedef struct Thread_Control_struct Thread_Control; |
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52 | #endif |
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53 | |
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54 | /** |
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55 | * @defgroup PerCPU RTEMS Per CPU Information |
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56 | * |
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57 | * @ingroup Score |
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58 | * |
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59 | * This defines the per CPU state information required by RTEMS |
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60 | * and the BSP. In an SMP configuration, there will be multiple |
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61 | * instances of this data structure -- one per CPU -- and the |
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62 | * current CPU number will be used as the index. |
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63 | */ |
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64 | |
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65 | /**@{*/ |
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66 | |
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67 | #if defined( RTEMS_SMP ) |
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68 | |
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69 | #if CPU_USE_DEFERRED_FP_SWITCH == TRUE |
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70 | #error "deferred FP switch not implemented for SMP" |
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71 | #endif |
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72 | |
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73 | /** |
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74 | * @brief State of a processor. |
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75 | * |
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76 | * The processor state controls the life cycle of processors at the lowest |
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77 | * level. No multi-threading or other high-level concepts matter here. |
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78 | * |
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79 | * State changes must be initiated via _Per_CPU_State_change(). This function |
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80 | * may not return in case someone requested a shutdown. The |
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81 | * _SMP_Send_message() function will be used to notify other processors about |
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82 | * state changes if the other processor is in the up state. |
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83 | * |
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84 | * Due to the sequential nature of the basic system initialization one |
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85 | * processor has a special role. It is the processor executing the boot_card() |
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86 | * function. This processor is called the boot processor. All other |
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87 | * processors are called secondary. |
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88 | * |
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89 | * @dot |
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90 | * digraph states { |
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91 | * i [label="PER_CPU_STATE_INITIAL"]; |
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92 | * rdy [label="PER_CPU_STATE_READY_TO_START_MULTITASKING"]; |
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93 | * reqsm [label="PER_CPU_STATE_REQUEST_START_MULTITASKING"]; |
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94 | * u [label="PER_CPU_STATE_UP"]; |
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95 | * s [label="PER_CPU_STATE_SHUTDOWN"]; |
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96 | * i -> rdy [label="processor\ncompleted initialization"]; |
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97 | * rdy -> reqsm [label="boot processor\ncompleted initialization"]; |
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98 | * reqsm -> u [label="processor\nstarts multitasking"]; |
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99 | * i -> s; |
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100 | * rdy -> s; |
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101 | * reqsm -> s; |
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102 | * u -> s; |
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103 | * } |
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104 | * @enddot |
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105 | */ |
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106 | typedef enum { |
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107 | /** |
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108 | * @brief The per CPU controls are initialized to zero. |
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109 | * |
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110 | * The boot processor executes the sequential boot code in this state. The |
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111 | * secondary processors should perform their basic initialization now and |
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112 | * change into the PER_CPU_STATE_READY_TO_START_MULTITASKING state once this |
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113 | * is complete. |
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114 | */ |
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115 | PER_CPU_STATE_INITIAL, |
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116 | |
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117 | /** |
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118 | * @brief Processor is ready to start multitasking. |
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119 | * |
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120 | * The secondary processor performed its basic initialization and is ready to |
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121 | * receive inter-processor interrupts. Interrupt delivery must be disabled |
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122 | * in this state, but requested inter-processor interrupts must be recorded |
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123 | * and must be delivered once the secondary processor enables interrupts for |
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124 | * the first time. The boot processor will wait for all secondary processors |
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125 | * to change into this state. In case a secondary processor does not reach |
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126 | * this state the system will not start. The secondary processors wait now |
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127 | * for a change into the PER_CPU_STATE_REQUEST_START_MULTITASKING state set |
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128 | * by the boot processor once all secondary processors reached the |
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129 | * PER_CPU_STATE_READY_TO_START_MULTITASKING state. |
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130 | */ |
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131 | PER_CPU_STATE_READY_TO_START_MULTITASKING, |
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132 | |
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133 | /** |
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134 | * @brief Multitasking start of processor is requested. |
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135 | * |
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136 | * The boot processor completed system initialization and is about to perform |
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137 | * a context switch to its heir thread. Secondary processors should now |
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138 | * issue a context switch to the heir thread. This normally enables |
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139 | * interrupts on the processor for the first time. |
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140 | */ |
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141 | PER_CPU_STATE_REQUEST_START_MULTITASKING, |
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142 | |
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143 | /** |
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144 | * @brief Normal multitasking state. |
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145 | */ |
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146 | PER_CPU_STATE_UP, |
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147 | |
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148 | /** |
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149 | * @brief This is the terminal state. |
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150 | */ |
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151 | PER_CPU_STATE_SHUTDOWN |
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152 | } Per_CPU_State; |
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153 | |
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154 | #endif /* defined( RTEMS_SMP ) */ |
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155 | |
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156 | /** |
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157 | * @brief Per CPU Core Structure |
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158 | * |
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159 | * This structure is used to hold per core state information. |
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160 | */ |
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161 | typedef struct { |
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162 | /** |
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163 | * @brief CPU port specific control. |
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164 | */ |
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165 | CPU_Per_CPU_control cpu_per_cpu; |
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166 | |
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167 | #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \ |
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168 | (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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169 | /** |
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170 | * This contains a pointer to the lower range of the interrupt stack for |
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171 | * this CPU. This is the address allocated and freed. |
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172 | */ |
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173 | void *interrupt_stack_low; |
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174 | |
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175 | /** |
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176 | * This contains a pointer to the interrupt stack pointer for this CPU. |
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177 | * It will be loaded at the beginning on an ISR. |
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178 | */ |
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179 | void *interrupt_stack_high; |
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180 | #endif |
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181 | |
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182 | /** |
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183 | * This contains the current interrupt nesting level on this |
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184 | * CPU. |
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185 | */ |
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186 | uint32_t isr_nest_level; |
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187 | |
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188 | /** |
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189 | * @brief The thread dispatch critical section nesting counter which is used |
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190 | * to prevent context switches at inopportune moments. |
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191 | */ |
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192 | volatile uint32_t thread_dispatch_disable_level; |
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193 | |
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194 | /** This is set to true when this CPU needs to run the dispatcher. */ |
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195 | volatile bool dispatch_necessary; |
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196 | |
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197 | /** This is the thread executing on this CPU. */ |
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198 | Thread_Control *executing; |
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199 | |
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200 | /** This is the heir thread for this this CPU. */ |
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201 | Thread_Control *heir; |
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202 | |
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203 | /** This is the time of the last context switch on this CPU. */ |
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204 | Timestamp_Control time_of_last_context_switch; |
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205 | |
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206 | /** |
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207 | * @brief This lock protects the dispatch_necessary, executing, heir and |
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208 | * message fields. |
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209 | */ |
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210 | ISR_lock_Control lock; |
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211 | |
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212 | #if defined( RTEMS_SMP ) |
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213 | /** |
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214 | * This is the request for the interrupt. |
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215 | * |
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216 | * @note This may become a chain protected by atomic instructions. |
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217 | */ |
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218 | uint32_t message; |
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219 | |
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220 | /** |
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221 | * @brief Indicates the current state of the CPU. |
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222 | * |
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223 | * This field is not protected by the _Per_CPU_State_lock lock. |
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224 | * |
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225 | * @see _Per_CPU_State_change(). |
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226 | */ |
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227 | Per_CPU_State state; |
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228 | #endif |
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229 | } Per_CPU_Control; |
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230 | |
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231 | #if defined( RTEMS_SMP ) |
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232 | typedef struct { |
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233 | Per_CPU_Control per_cpu; |
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234 | char unused_space_for_cache_line_alignment |
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235 | [ PER_CPU_CONTROL_SIZE - sizeof( Per_CPU_Control ) ]; |
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236 | } Per_CPU_Control_envelope; |
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237 | #else |
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238 | typedef struct { |
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239 | Per_CPU_Control per_cpu; |
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240 | } Per_CPU_Control_envelope; |
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241 | #endif |
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242 | |
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243 | /** |
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244 | * @brief Set of Per CPU Core Information |
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245 | * |
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246 | * This is an array of per CPU core information. |
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247 | */ |
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248 | extern Per_CPU_Control_envelope _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT; |
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249 | |
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250 | #define _Per_CPU_ISR_disable_and_acquire( per_cpu, isr_cookie ) \ |
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251 | _ISR_lock_ISR_disable_and_acquire( &( per_cpu )->lock, isr_cookie ) |
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252 | |
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253 | #define _Per_CPU_Release_and_ISR_enable( per_cpu, isr_cookie ) \ |
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254 | _ISR_lock_Release_and_ISR_enable( &( per_cpu )->lock, isr_cookie ) |
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255 | |
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256 | #define _Per_CPU_Acquire( per_cpu ) \ |
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257 | _ISR_lock_Acquire( &( per_cpu )->lock ) |
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258 | |
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259 | #define _Per_CPU_Release( per_cpu ) \ |
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260 | _ISR_lock_Release( &( per_cpu )->lock ) |
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261 | |
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262 | #if defined( RTEMS_SMP ) |
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263 | #define _Per_CPU_Acquire_all( isr_cookie ) \ |
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264 | do { \ |
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265 | uint32_t ncpus = _SMP_Get_processor_count(); \ |
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266 | uint32_t cpu; \ |
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267 | _ISR_Disable( isr_cookie ); \ |
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268 | for ( cpu = 0 ; cpu < ncpus ; ++cpu ) { \ |
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269 | _Per_CPU_Acquire( _Per_CPU_Get_by_index( cpu ) ); \ |
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270 | } \ |
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271 | } while ( 0 ) |
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272 | #else |
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273 | #define _Per_CPU_Acquire_all( isr_cookie ) \ |
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274 | _ISR_Disable( isr_cookie ) |
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275 | #endif |
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276 | |
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277 | #if defined( RTEMS_SMP ) |
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278 | #define _Per_CPU_Release_all( isr_cookie ) \ |
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279 | do { \ |
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280 | uint32_t ncpus = _SMP_Get_processor_count(); \ |
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281 | uint32_t cpu; \ |
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282 | for ( cpu = 0 ; cpu < ncpus ; ++cpu ) { \ |
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283 | _Per_CPU_Release( _Per_CPU_Get_by_index( cpu ) ); \ |
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284 | } \ |
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285 | _ISR_Enable( isr_cookie ); \ |
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286 | } while ( 0 ) |
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287 | #else |
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288 | #define _Per_CPU_Release_all( isr_cookie ) \ |
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289 | _ISR_Enable( isr_cookie ) |
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290 | #endif |
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291 | |
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292 | #if defined( RTEMS_SMP ) |
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293 | static inline Per_CPU_Control *_Per_CPU_Get( void ) |
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294 | { |
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295 | Per_CPU_Control *per_cpu = |
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296 | &_Per_CPU_Information[ _SMP_Get_current_processor() ].per_cpu; |
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297 | |
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298 | _Assert( |
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299 | per_cpu->thread_dispatch_disable_level != 0 || _ISR_Get_level() != 0 |
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300 | ); |
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301 | |
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302 | return per_cpu; |
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303 | } |
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304 | #else |
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305 | #define _Per_CPU_Get() ( &_Per_CPU_Information[ 0 ].per_cpu ) |
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306 | #endif |
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307 | |
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308 | static inline Per_CPU_Control *_Per_CPU_Get_by_index( uint32_t index ) |
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309 | { |
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310 | return &_Per_CPU_Information[ index ].per_cpu; |
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311 | } |
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312 | |
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313 | static inline uint32_t _Per_CPU_Get_index( const Per_CPU_Control *per_cpu ) |
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314 | { |
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315 | const Per_CPU_Control_envelope *per_cpu_envelope = |
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316 | ( const Per_CPU_Control_envelope * ) per_cpu; |
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317 | |
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318 | return ( uint32_t ) ( per_cpu_envelope - &_Per_CPU_Information[ 0 ] ); |
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319 | } |
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320 | |
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321 | #if defined( RTEMS_SMP ) |
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322 | |
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323 | static inline void _Per_CPU_Send_interrupt( const Per_CPU_Control *per_cpu ) |
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324 | { |
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325 | _CPU_SMP_Send_interrupt( _Per_CPU_Get_index( per_cpu ) ); |
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326 | } |
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327 | |
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328 | /** |
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329 | * @brief Allocate and Initialize Per CPU Structures |
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330 | * |
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331 | * This method allocates and initialize the per CPU structure. |
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332 | */ |
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333 | void _Per_CPU_Initialize(void); |
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334 | |
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335 | void _Per_CPU_State_change( |
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336 | Per_CPU_Control *per_cpu, |
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337 | Per_CPU_State new_state |
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338 | ); |
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339 | |
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340 | #endif /* defined( RTEMS_SMP ) */ |
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341 | |
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342 | /* |
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343 | * On a non SMP system, the _SMP_Get_current_processor() is defined to 0. |
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344 | * Thus when built for non-SMP, there should be no performance penalty. |
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345 | */ |
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346 | #define _Thread_Dispatch_disable_level \ |
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347 | _Per_CPU_Get()->thread_dispatch_disable_level |
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348 | #define _Thread_Heir \ |
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349 | _Per_CPU_Get()->heir |
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350 | #define _Thread_Executing \ |
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351 | _Per_CPU_Get()->executing |
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352 | #define _ISR_Nest_level \ |
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353 | _Per_CPU_Get()->isr_nest_level |
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354 | #define _CPU_Interrupt_stack_low \ |
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355 | _Per_CPU_Get()->interrupt_stack_low |
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356 | #define _CPU_Interrupt_stack_high \ |
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357 | _Per_CPU_Get()->interrupt_stack_high |
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358 | #define _Thread_Dispatch_necessary \ |
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359 | _Per_CPU_Get()->dispatch_necessary |
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360 | #define _Thread_Time_of_last_context_switch \ |
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361 | _Per_CPU_Get()->time_of_last_context_switch |
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362 | |
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363 | /**@}*/ |
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364 | |
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365 | #endif /* !defined( ASM ) */ |
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366 | |
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367 | #if defined( ASM ) || defined( _RTEMS_PERCPU_DEFINE_OFFSETS ) |
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368 | |
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369 | #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \ |
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370 | (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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371 | /* |
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372 | * If this CPU target lets RTEMS allocates the interrupt stack, then |
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373 | * we need to have places in the per CPU table to hold them. |
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374 | */ |
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375 | #define PER_CPU_INTERRUPT_STACK_LOW \ |
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376 | CPU_PER_CPU_CONTROL_SIZE |
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377 | #define PER_CPU_INTERRUPT_STACK_HIGH \ |
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378 | PER_CPU_INTERRUPT_STACK_LOW + CPU_SIZEOF_POINTER |
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379 | #define PER_CPU_END_STACK \ |
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380 | PER_CPU_INTERRUPT_STACK_HIGH + CPU_SIZEOF_POINTER |
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381 | |
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382 | #define INTERRUPT_STACK_LOW \ |
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383 | (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_LOW) |
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384 | #define INTERRUPT_STACK_HIGH \ |
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385 | (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_HIGH) |
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386 | #else |
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387 | #define PER_CPU_END_STACK \ |
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388 | CPU_PER_CPU_CONTROL_SIZE |
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389 | #endif |
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390 | |
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391 | /* |
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392 | * These are the offsets of the required elements in the per CPU table. |
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393 | */ |
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394 | #define PER_CPU_ISR_NEST_LEVEL \ |
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395 | PER_CPU_END_STACK |
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396 | #define PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL \ |
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397 | PER_CPU_ISR_NEST_LEVEL + 4 |
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398 | #define PER_CPU_DISPATCH_NEEDED \ |
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399 | PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL + 4 |
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400 | |
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401 | #define THREAD_DISPATCH_DISABLE_LEVEL \ |
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402 | (SYM(_Per_CPU_Information) + PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL) |
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403 | #define ISR_NEST_LEVEL \ |
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404 | (SYM(_Per_CPU_Information) + PER_CPU_ISR_NEST_LEVEL) |
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405 | #define DISPATCH_NEEDED \ |
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406 | (SYM(_Per_CPU_Information) + PER_CPU_DISPATCH_NEEDED) |
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407 | |
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408 | #endif /* defined( ASM ) || defined( _RTEMS_PERCPU_DEFINE_OFFSETS ) */ |
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409 | |
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410 | #ifdef __cplusplus |
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411 | } |
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412 | #endif |
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413 | |
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414 | #endif |
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415 | /* end of include file */ |
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