1 | /** |
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2 | * @file rtems/score/percpu.h |
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3 | * |
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4 | * This include file defines the per CPU information required |
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5 | * by RTEMS. |
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6 | */ |
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7 | |
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8 | /* |
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9 | * COPYRIGHT (c) 1989-2011. |
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10 | * On-Line Applications Research Corporation (OAR). |
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11 | * |
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12 | * The license and distribution terms for this file may be |
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13 | * found in the file LICENSE in this distribution or at |
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14 | * http://www.rtems.com/license/LICENSE. |
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15 | */ |
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16 | |
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17 | #ifndef _RTEMS_PERCPU_H |
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18 | #define _RTEMS_PERCPU_H |
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19 | |
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20 | #include <rtems/score/cpu.h> |
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21 | |
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22 | #ifdef ASM |
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23 | #include <rtems/asm.h> |
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24 | #else |
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25 | #include <rtems/score/isrlevel.h> |
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26 | #include <rtems/score/timestamp.h> |
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27 | #if defined(RTEMS_SMP) |
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28 | #include <rtems/score/smplock.h> |
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29 | #endif |
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30 | |
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31 | /* |
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32 | * NOTE: This file MUST be included on non-smp systems as well |
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33 | * in order to define bsp_smp_processor_id. |
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34 | */ |
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35 | #include <rtems/bspsmp.h> |
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36 | #endif |
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37 | |
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38 | /** |
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39 | * @defgroup PerCPU RTEMS Per CPU Information |
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40 | * |
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41 | * @ingroup Score |
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42 | * |
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43 | * This defines the per CPU state information required by RTEMS |
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44 | * and the BSP. In an SMP configuration, there will be multiple |
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45 | * instances of this data structure -- one per CPU -- and the |
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46 | * current CPU number will be used as the index. |
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47 | */ |
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48 | |
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49 | /**@{*/ |
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50 | |
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51 | #ifdef __cplusplus |
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52 | extern "C" { |
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53 | #endif |
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54 | |
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55 | #ifndef ASM |
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56 | #include <rtems/score/timestamp.h> |
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57 | |
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58 | #ifndef __THREAD_CONTROL_DEFINED__ |
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59 | #define __THREAD_CONTROL_DEFINED__ |
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60 | typedef struct Thread_Control_struct Thread_Control; |
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61 | #endif |
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62 | |
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63 | typedef enum { |
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64 | |
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65 | /** |
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66 | * This defines the constant used to indicate that the cpu code is in |
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67 | * its initial powered up start. |
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68 | */ |
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69 | RTEMS_BSP_SMP_CPU_INITIAL_STATE = 1, |
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70 | |
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71 | /** |
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72 | * This defines the constant used to indicate that the cpu code has |
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73 | * completed basic initialization and awaits further commands. |
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74 | */ |
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75 | RTEMS_BSP_SMP_CPU_INITIALIZED = 2, |
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76 | |
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77 | /** |
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78 | * This defines the constant used to indicate that the cpu code has |
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79 | * completed basic initialization and awaits further commands. |
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80 | */ |
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81 | RTEMS_BSP_SMP_CPU_UP = 3, |
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82 | |
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83 | /** |
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84 | * This defines the constant used to indicate that the cpu code has |
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85 | * shut itself down. |
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86 | */ |
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87 | RTEMS_BSP_SMP_CPU_SHUTDOWN = 4 |
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88 | } bsp_smp_cpu_state; |
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89 | |
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90 | /** |
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91 | * @brief Per CPU Core Structure |
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92 | * |
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93 | * This structure is used to hold per core state information. |
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94 | */ |
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95 | typedef struct { |
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96 | #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \ |
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97 | (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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98 | /** |
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99 | * This contains a pointer to the lower range of the interrupt stack for |
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100 | * this CPU. This is the address allocated and freed. |
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101 | */ |
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102 | void *interrupt_stack_low; |
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103 | |
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104 | /** |
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105 | * This contains a pointer to the interrupt stack pointer for this CPU. |
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106 | * It will be loaded at the beginning on an ISR. |
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107 | */ |
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108 | void *interrupt_stack_high; |
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109 | #endif |
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110 | |
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111 | /** |
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112 | * This contains the current interrupt nesting level on this |
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113 | * CPU. |
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114 | */ |
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115 | uint32_t isr_nest_level; |
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116 | |
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117 | /** This is set to true when this CPU needs to run the dispatcher. */ |
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118 | volatile bool dispatch_necessary; |
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119 | |
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120 | /** This is the thread executing on this CPU. */ |
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121 | Thread_Control *executing; |
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122 | |
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123 | /** This is the heir thread for this this CPU. */ |
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124 | Thread_Control *heir; |
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125 | |
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126 | /** This is the idle thread for this CPU. */ |
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127 | Thread_Control *idle; |
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128 | |
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129 | /** This is the time of the last context switch on this CPU. */ |
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130 | Timestamp_Control time_of_last_context_switch; |
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131 | |
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132 | #if defined(RTEMS_SMP) |
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133 | /** This element is used to lock this structure */ |
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134 | SMP_lock_spinlock_simple_Control lock; |
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135 | |
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136 | /** This indicates that the CPU is online. */ |
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137 | uint32_t state; |
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138 | |
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139 | /** |
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140 | * This is the request for the interrupt. |
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141 | * |
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142 | * @note This may become a chain protected by atomic instructions. |
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143 | */ |
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144 | uint32_t message; |
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145 | #endif |
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146 | } Per_CPU_Control; |
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147 | #endif |
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148 | |
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149 | #if defined(ASM) || defined(_RTEMS_PERCPU_DEFINE_OFFSETS) |
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150 | |
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151 | #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \ |
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152 | (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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153 | /* |
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154 | * If this CPU target lets RTEMS allocates the interrupt stack, then |
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155 | * we need to have places in the per CPU table to hold them. |
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156 | */ |
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157 | #define PER_CPU_INTERRUPT_STACK_LOW \ |
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158 | 0 |
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159 | #define PER_CPU_INTERRUPT_STACK_HIGH \ |
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160 | PER_CPU_INTERRUPT_STACK_LOW + CPU_SIZEOF_POINTER |
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161 | #define PER_CPU_END_STACK \ |
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162 | PER_CPU_INTERRUPT_STACK_HIGH + CPU_SIZEOF_POINTER |
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163 | |
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164 | #define INTERRUPT_STACK_LOW \ |
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165 | (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_LOW) |
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166 | #define INTERRUPT_STACK_HIGH \ |
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167 | (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_HIGH) |
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168 | #else |
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169 | #define PER_CPU_END_STACK \ |
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170 | 0 |
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171 | #endif |
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172 | |
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173 | /* |
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174 | * These are the offsets of the required elements in the per CPU table. |
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175 | */ |
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176 | #define PER_CPU_ISR_NEST_LEVEL \ |
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177 | PER_CPU_END_STACK |
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178 | #define PER_CPU_DISPATCH_NEEDED \ |
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179 | PER_CPU_ISR_NEST_LEVEL + 4 |
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180 | |
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181 | #define ISR_NEST_LEVEL \ |
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182 | (SYM(_Per_CPU_Information) + PER_CPU_ISR_NEST_LEVEL) |
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183 | #define DISPATCH_NEEDED \ |
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184 | (SYM(_Per_CPU_Information) + PER_CPU_DISPATCH_NEEDED) |
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185 | |
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186 | #endif /* defined(ASM) || defined(_RTEMS_PERCPU_DEFINE_OFFSETS) */ |
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187 | |
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188 | #ifndef ASM |
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189 | |
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190 | /** |
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191 | * @brief Set of Per CPU Core Information |
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192 | * |
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193 | * This is an array of per CPU core information. |
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194 | */ |
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195 | extern Per_CPU_Control _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT; |
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196 | |
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197 | #if defined(RTEMS_SMP) |
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198 | /** |
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199 | * @brief Set of Pointers to Per CPU Core Information |
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200 | * |
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201 | * This is an array of pointers to each CPU's per CPU data structure. |
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202 | * It should be simpler to retrieve this pointer in assembly language |
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203 | * that to calculate the array offset. |
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204 | */ |
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205 | extern Per_CPU_Control *_Per_CPU_Information_p[]; |
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206 | |
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207 | /** |
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208 | * @brief Initialize SMP Handler |
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209 | * |
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210 | * This method initialize the SMP Handler. |
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211 | */ |
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212 | void _SMP_Handler_initialize(void); |
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213 | |
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214 | /** |
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215 | * @brief Allocate and Initialize Per CPU Structures |
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216 | * |
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217 | * This method allocates and initialize the per CPU structure. |
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218 | */ |
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219 | void _Per_CPU_Initialize(void); |
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220 | |
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221 | #endif |
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222 | |
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223 | /* |
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224 | * On a non SMP system, the bsp_smp_processor_id is defined to 0. |
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225 | * Thus when built for non-SMP, there should be no performance penalty. |
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226 | */ |
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227 | #define _Thread_Heir \ |
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228 | _Per_CPU_Information[bsp_smp_processor_id()].heir |
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229 | #define _Thread_Executing \ |
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230 | _Per_CPU_Information[bsp_smp_processor_id()].executing |
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231 | #define _Thread_Idle \ |
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232 | _Per_CPU_Information[bsp_smp_processor_id()].idle |
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233 | #define _ISR_Nest_level \ |
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234 | _Per_CPU_Information[bsp_smp_processor_id()].isr_nest_level |
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235 | #define _CPU_Interrupt_stack_low \ |
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236 | _Per_CPU_Information[bsp_smp_processor_id()].interrupt_stack_low |
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237 | #define _CPU_Interrupt_stack_high \ |
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238 | _Per_CPU_Information[bsp_smp_processor_id()].interrupt_stack_high |
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239 | #define _Thread_Dispatch_necessary \ |
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240 | _Per_CPU_Information[bsp_smp_processor_id()].dispatch_necessary |
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241 | #define _Thread_Time_of_last_context_switch \ |
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242 | _Per_CPU_Information[bsp_smp_processor_id()].time_of_last_context_switch |
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243 | |
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244 | #endif /* ASM */ |
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245 | |
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246 | #ifdef __cplusplus |
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247 | } |
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248 | #endif |
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249 | |
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250 | /**@}*/ |
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251 | |
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252 | #endif |
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253 | /* end of include file */ |
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