source: rtems/cpukit/score/include/rtems/score/percpu.h @ 10643e9

4.115
Last change on this file since 10643e9 was 10643e9, checked in by Sebastian Huber <sebastian.huber@…>, on May 13, 2013 at 1:44:02 PM

smp: Make CPU_ALLOCATE_INTERRUPT_STACK optional

  • Property mode set to 100644
File size: 6.5 KB
Line 
1/**
2 *  @file  rtems/score/percpu.h
3 *
4 *  This include file defines the per CPU information required
5 *  by RTEMS.
6 */
7
8/*
9 *  COPYRIGHT (c) 1989-2011.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 */
16
17#ifndef _RTEMS_PERCPU_H
18#define _RTEMS_PERCPU_H
19
20#include <rtems/score/cpu.h>
21
22#ifdef ASM
23  #include <rtems/asm.h>
24#else
25  #include <rtems/score/isrlevel.h>
26  #include <rtems/score/timestamp.h>
27  #if defined(RTEMS_SMP)
28    #include <rtems/score/smplock.h>
29  #endif
30
31  /*
32   * NOTE: This file MUST be included on non-smp systems as well
33   *       in order to define bsp_smp_processor_id.
34   */
35  #include <rtems/bspsmp.h>
36#endif
37
38/**
39 *  @defgroup PerCPU RTEMS Per CPU Information
40 *
41 *  @ingroup Score
42 *
43 *  This defines the per CPU state information required by RTEMS
44 *  and the BSP.  In an SMP configuration, there will be multiple
45 *  instances of this data structure -- one per CPU -- and the
46 *  current CPU number will be used as the index.
47 */
48
49/**@{*/
50
51#ifdef __cplusplus
52extern "C" {
53#endif
54
55#ifndef ASM
56#include <rtems/score/timestamp.h>
57
58#ifndef __THREAD_CONTROL_DEFINED__
59#define __THREAD_CONTROL_DEFINED__
60typedef struct Thread_Control_struct Thread_Control;
61#endif
62
63typedef enum {
64
65  /**
66   *  This defines the constant used to indicate that the cpu code is in
67   *  its initial powered up start.
68   */
69   RTEMS_BSP_SMP_CPU_INITIAL_STATE = 1,
70
71  /**
72   *  This defines the constant used to indicate that the cpu code has
73   *  completed basic initialization and awaits further commands.
74   */
75   RTEMS_BSP_SMP_CPU_INITIALIZED = 2,
76
77  /**
78   *  This defines the constant used to indicate that the cpu code has
79   *  completed basic initialization and awaits further commands.
80   */
81  RTEMS_BSP_SMP_CPU_UP = 3,
82
83  /**
84   *  This defines the constant used to indicate that the cpu code has
85   *  shut itself down.
86   */
87  RTEMS_BSP_SMP_CPU_SHUTDOWN = 4
88} bsp_smp_cpu_state;
89
90/**
91 *  @brief Per CPU Core Structure
92 *
93 *  This structure is used to hold per core state information.
94 */
95typedef struct {
96  #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
97      (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
98    /**
99     * This contains a pointer to the lower range of the interrupt stack for
100     * this CPU.  This is the address allocated and freed.
101     */
102    void  *interrupt_stack_low;
103
104    /**
105     * This contains a pointer to the interrupt stack pointer for this CPU.
106     * It will be loaded at the beginning on an ISR.
107     */
108    void  *interrupt_stack_high;
109  #endif
110
111  /**
112   *  This contains the current interrupt nesting level on this
113   *  CPU.
114   */
115  uint32_t isr_nest_level;
116
117  /** This is set to true when this CPU needs to run the dispatcher. */
118  volatile bool dispatch_necessary;
119
120  /** This is the thread executing on this CPU. */
121  Thread_Control *executing;
122
123  /** This is the heir thread for this this CPU. */
124  Thread_Control *heir;
125
126  /** This is the idle thread for this CPU. */
127  Thread_Control *idle;
128
129  /** This is the time of the last context switch on this CPU. */
130  Timestamp_Control time_of_last_context_switch;
131
132  #if defined(RTEMS_SMP)
133    /** This element is used to lock this structure */
134    SMP_lock_spinlock_simple_Control  lock;
135
136    /** This indicates that the CPU is online. */
137    uint32_t                          state;
138
139    /**
140     *  This is the request for the interrupt.
141     *
142     *  @note This may become a chain protected by atomic instructions.
143     */
144    uint32_t                          message;
145  #endif
146} Per_CPU_Control;
147#endif
148
149#if defined(ASM) || defined(_RTEMS_PERCPU_DEFINE_OFFSETS)
150
151#if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \
152    (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
153  /*
154   *  If this CPU target lets RTEMS allocates the interrupt stack, then
155   *  we need to have places in the per CPU table to hold them.
156   */
157  #define PER_CPU_INTERRUPT_STACK_LOW \
158    0
159  #define PER_CPU_INTERRUPT_STACK_HIGH \
160    PER_CPU_INTERRUPT_STACK_LOW + CPU_SIZEOF_POINTER
161  #define PER_CPU_END_STACK             \
162    PER_CPU_INTERRUPT_STACK_HIGH + CPU_SIZEOF_POINTER
163
164  #define INTERRUPT_STACK_LOW \
165    (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_LOW)
166  #define INTERRUPT_STACK_HIGH \
167    (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_HIGH)
168#else
169  #define PER_CPU_END_STACK \
170    0
171#endif
172
173/*
174 *  These are the offsets of the required elements in the per CPU table.
175 */
176#define PER_CPU_ISR_NEST_LEVEL \
177  PER_CPU_END_STACK
178#define PER_CPU_DISPATCH_NEEDED \
179  PER_CPU_ISR_NEST_LEVEL + 4
180
181#define ISR_NEST_LEVEL \
182  (SYM(_Per_CPU_Information) + PER_CPU_ISR_NEST_LEVEL)
183#define DISPATCH_NEEDED \
184  (SYM(_Per_CPU_Information) + PER_CPU_DISPATCH_NEEDED)
185
186#endif /* defined(ASM) || defined(_RTEMS_PERCPU_DEFINE_OFFSETS) */
187
188#ifndef ASM
189
190/**
191 *  @brief Set of Per CPU Core Information
192 *
193 *  This is an array of per CPU core information.
194 */
195extern Per_CPU_Control _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT;
196
197#if defined(RTEMS_SMP)
198/**
199 *  @brief Set of Pointers to Per CPU Core Information
200 *
201 *  This is an array of pointers to each CPU's per CPU data structure.
202 *  It should be simpler to retrieve this pointer in assembly language
203 *  that to calculate the array offset.
204 */
205extern Per_CPU_Control *_Per_CPU_Information_p[];
206
207/**
208 *  @brief Initialize SMP Handler
209 *
210 *  This method initialize the SMP Handler.
211 */
212void _SMP_Handler_initialize(void);
213
214/**
215 *  @brief Allocate and Initialize Per CPU Structures
216 *
217 *  This method allocates and initialize the per CPU structure.
218 */
219void _Per_CPU_Initialize(void);
220
221#endif
222
223/*
224 * On a non SMP system, the bsp_smp_processor_id is defined to 0.
225 * Thus when built for non-SMP, there should be no performance penalty.
226 */
227#define _Thread_Heir \
228  _Per_CPU_Information[bsp_smp_processor_id()].heir
229#define _Thread_Executing \
230  _Per_CPU_Information[bsp_smp_processor_id()].executing
231#define _Thread_Idle \
232  _Per_CPU_Information[bsp_smp_processor_id()].idle
233#define _ISR_Nest_level \
234  _Per_CPU_Information[bsp_smp_processor_id()].isr_nest_level
235#define _CPU_Interrupt_stack_low \
236  _Per_CPU_Information[bsp_smp_processor_id()].interrupt_stack_low
237#define _CPU_Interrupt_stack_high \
238  _Per_CPU_Information[bsp_smp_processor_id()].interrupt_stack_high
239#define _Thread_Dispatch_necessary \
240  _Per_CPU_Information[bsp_smp_processor_id()].dispatch_necessary
241#define _Thread_Time_of_last_context_switch \
242  _Per_CPU_Information[bsp_smp_processor_id()].time_of_last_context_switch
243
244#endif  /* ASM */
245
246#ifdef __cplusplus
247}
248#endif
249
250/**@}*/
251
252#endif
253/* end of include file */
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