[11e8bc5] | 1 | /** |
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| 2 | * @file rtems/score/percpu.h |
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| 3 | * |
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| 4 | * This include file defines the per CPU information required |
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| 5 | * by RTEMS. |
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| 6 | */ |
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| 7 | |
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| 8 | /* |
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[06dcaf0] | 9 | * COPYRIGHT (c) 1989-2011. |
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[11e8bc5] | 10 | * On-Line Applications Research Corporation (OAR). |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.rtems.com/license/LICENSE. |
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| 15 | * |
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[dacdda30] | 16 | * $Id$ |
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[11e8bc5] | 17 | */ |
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| 18 | |
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| 19 | #ifndef _RTEMS_PERCPU_H |
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| 20 | #define _RTEMS_PERCPU_H |
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| 21 | |
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[9f9a82b] | 22 | #include <rtems/score/cpu.h> |
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| 23 | |
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[11e8bc5] | 24 | #ifdef ASM |
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| 25 | #include <rtems/asm.h> |
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[06dcaf0] | 26 | #else |
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[df00777] | 27 | #include <rtems/score/isrlevel.h> |
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[0a101d57] | 28 | #include <rtems/score/timestamp.h> |
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[06dcaf0] | 29 | #if defined(RTEMS_SMP) |
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| 30 | #include <rtems/score/smplock.h> |
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| 31 | #endif |
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[42bb344e] | 32 | |
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| 33 | /* |
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| 34 | * NOTE: This file MUST be included on non-smp systems as well |
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| 35 | * in order to define bsp_smp_processor_id. |
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| 36 | */ |
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[06dcaf0] | 37 | #include <rtems/bspsmp.h> |
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[11e8bc5] | 38 | #endif |
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| 39 | |
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| 40 | /** |
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| 41 | * @defgroup PerCPU RTEMS Per CPU Information |
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| 42 | * |
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[d8cd045c] | 43 | * @ingroup Score |
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| 44 | * |
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[11e8bc5] | 45 | * This defines the per CPU state information required by RTEMS |
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| 46 | * and the BSP. In an SMP configuration, there will be multiple |
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| 47 | * instances of this data structure -- one per CPU -- and the |
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| 48 | * current CPU number will be used as the index. |
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| 49 | */ |
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| 50 | |
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| 51 | /**@{*/ |
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| 52 | |
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| 53 | #ifdef __cplusplus |
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| 54 | extern "C" { |
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| 55 | #endif |
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| 56 | |
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| 57 | #ifndef ASM |
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[0a101d57] | 58 | #include <rtems/score/timestamp.h> |
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| 59 | |
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[06dcaf0] | 60 | #ifndef __THREAD_CONTROL_DEFINED__ |
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| 61 | #define __THREAD_CONTROL_DEFINED__ |
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[11e8bc5] | 62 | typedef struct Thread_Control_struct Thread_Control; |
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[06dcaf0] | 63 | #endif |
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| 64 | |
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| 65 | #if (CPU_ALLOCATE_INTERRUPT_STACK == FALSE) && defined(RTEMS_SMP) |
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| 66 | #error "RTEMS must allocate per CPU interrupt stack for SMP" |
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| 67 | #endif |
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| 68 | |
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| 69 | typedef enum { |
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[dacdda30] | 70 | |
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[06dcaf0] | 71 | /** |
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| 72 | * This defines the constant used to indicate that the cpu code is in |
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| 73 | * its initial powered up start. |
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| 74 | */ |
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| 75 | RTEMS_BSP_SMP_CPU_INITIAL_STATE = 1, |
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| 76 | |
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| 77 | /** |
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| 78 | * This defines the constant used to indicate that the cpu code has |
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| 79 | * completed basic initialization and awaits further commands. |
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| 80 | */ |
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| 81 | RTEMS_BSP_SMP_CPU_INITIALIZED = 2, |
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| 82 | |
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[d4dc7c8] | 83 | /** |
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| 84 | * This defines the constant used to indicate that the cpu code has |
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| 85 | * completed basic initialization and awaits further commands. |
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| 86 | */ |
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| 87 | RTEMS_BSP_SMP_CPU_UP = 3, |
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| 88 | |
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[06dcaf0] | 89 | /** |
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| 90 | * This defines the constant used to indicate that the cpu code has |
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| 91 | * shut itself down. |
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| 92 | */ |
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[d4dc7c8] | 93 | RTEMS_BSP_SMP_CPU_SHUTDOWN = 4 |
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[06dcaf0] | 94 | } bsp_smp_cpu_state; |
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[11e8bc5] | 95 | |
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| 96 | /** |
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| 97 | * @brief Per CPU Core Structure |
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| 98 | * |
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| 99 | * This structure is used to hold per core state information. |
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| 100 | */ |
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| 101 | typedef struct { |
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[06dcaf0] | 102 | #if defined(RTEMS_SMP) |
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| 103 | /** This element is used to lock this structure */ |
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[dacdda30] | 104 | SMP_lock_spinlock_simple_Control lock; |
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[06dcaf0] | 105 | |
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| 106 | /** This indicates that the CPU is online. */ |
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[dacdda30] | 107 | uint32_t state; |
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[06dcaf0] | 108 | |
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| 109 | /** |
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| 110 | * This is the request for the interrupt. |
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[dacdda30] | 111 | * |
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[06dcaf0] | 112 | * @note This may become a chain protected by atomic instructions. |
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| 113 | */ |
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[dacdda30] | 114 | uint32_t message; |
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[06dcaf0] | 115 | #endif |
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| 116 | |
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[11e8bc5] | 117 | #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \ |
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| 118 | (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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| 119 | /** |
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| 120 | * This contains a pointer to the lower range of the interrupt stack for |
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| 121 | * this CPU. This is the address allocated and freed. |
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| 122 | */ |
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| 123 | void *interrupt_stack_low; |
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| 124 | |
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| 125 | /** |
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| 126 | * This contains a pointer to the interrupt stack pointer for this CPU. |
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| 127 | * It will be loaded at the beginning on an ISR. |
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| 128 | */ |
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| 129 | void *interrupt_stack_high; |
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| 130 | #endif |
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| 131 | |
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| 132 | /** |
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| 133 | * This contains the current interrupt nesting level on this |
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| 134 | * CPU. |
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| 135 | */ |
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| 136 | uint32_t isr_nest_level; |
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| 137 | |
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| 138 | /** This is the thread executing on this CPU. */ |
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| 139 | Thread_Control *executing; |
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| 140 | |
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| 141 | /** This is the heir thread for this this CPU. */ |
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| 142 | Thread_Control *heir; |
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| 143 | |
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| 144 | /** This is the idle thread for this CPU. */ |
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| 145 | Thread_Control *idle; |
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| 146 | |
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| 147 | /** This is set to true when this CPU needs to run the dispatcher. */ |
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[4b1d261] | 148 | volatile bool dispatch_necessary; |
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[11e8bc5] | 149 | |
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[0a101d57] | 150 | /** This is the time of the last context switch on this CPU. */ |
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| 151 | Timestamp_Control time_of_last_context_switch; |
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[11e8bc5] | 152 | } Per_CPU_Control; |
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| 153 | #endif |
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| 154 | |
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| 155 | #ifdef ASM |
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[06dcaf0] | 156 | #if defined(RTEMS_SMP) |
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| 157 | #define PER_CPU_LOCK 0 |
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| 158 | #define PER_CPU_STATE (1 * __RTEMS_SIZEOF_VOID_P__) |
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| 159 | #define PER_CPU_MESSAGE (2 * __RTEMS_SIZEOF_VOID_P__) |
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| 160 | #define PER_CPU_END_SMP (3 * __RTEMS_SIZEOF_VOID_P__) |
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| 161 | #else |
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| 162 | #define PER_CPU_END_SMP 0 |
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| 163 | #endif |
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[11e8bc5] | 164 | |
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| 165 | #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \ |
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| 166 | (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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| 167 | /* |
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| 168 | * If this CPU target lets RTEMS allocates the interrupt stack, then |
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| 169 | * we need to have places in the per cpu table to hold them. |
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| 170 | */ |
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[06dcaf0] | 171 | #define PER_CPU_INTERRUPT_STACK_LOW PER_CPU_END_SMP |
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| 172 | #define PER_CPU_INTERRUPT_STACK_HIGH \ |
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| 173 | PER_CPU_INTERRUPT_STACK_LOW + (1 * __RTEMS_SIZEOF_VOID_P__) |
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| 174 | #define PER_CPU_END_STACK \ |
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| 175 | PER_CPU_INTERRUPT_STACK_HIGH + (1 * __RTEMS_SIZEOF_VOID_P__) |
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[11e8bc5] | 176 | #else |
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[06dcaf0] | 177 | #define PER_CPU_END_STACK PER_CPU_END_SMP |
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[11e8bc5] | 178 | #endif |
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| 179 | |
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| 180 | /* |
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| 181 | * These are the offsets of the required elements in the per CPU table. |
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| 182 | */ |
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[263ab4b] | 183 | #define PER_CPU_ISR_NEST_LEVEL \ |
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| 184 | PER_CPU_END_STACK + 0 |
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| 185 | #define PER_CPU_EXECUTING \ |
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| 186 | PER_CPU_END_STACK + (1 * __RTEMS_SIZEOF_VOID_P__) |
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| 187 | #define PER_CPU_HEIR \ |
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| 188 | PER_CPU_END_STACK + (2 * __RTEMS_SIZEOF_VOID_P__) |
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| 189 | #define PER_CPU_IDLE \ |
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| 190 | PER_CPU_END_STACK + (3 * __RTEMS_SIZEOF_VOID_P__) |
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| 191 | #define PER_CPU_DISPATCH_NEEDED \ |
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| 192 | PER_CPU_END_STACK + (4 * __RTEMS_SIZEOF_VOID_P__) |
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| 193 | |
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[11e8bc5] | 194 | #define ISR_NEST_LEVEL \ |
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[263ab4b] | 195 | (SYM(_Per_CPU_Information) + PER_CPU_ISR_NEST_LEVEL) |
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[11e8bc5] | 196 | #define DISPATCH_NEEDED \ |
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[263ab4b] | 197 | (SYM(_Per_CPU_Information) + PER_CPU_DISPATCH_NEEDED) |
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[11e8bc5] | 198 | |
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| 199 | /* |
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| 200 | * Do not define these offsets if they are not in the table. |
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| 201 | */ |
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| 202 | #if (CPU_ALLOCATE_INTERRUPT_STACK == TRUE) || \ |
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| 203 | (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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| 204 | #define INTERRUPT_STACK_LOW \ |
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| 205 | (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_LOW) |
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| 206 | #define INTERRUPT_STACK_HIGH \ |
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| 207 | (SYM(_Per_CPU_Information) + PER_CPU_INTERRUPT_STACK_HIGH) |
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| 208 | #endif |
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| 209 | |
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| 210 | #endif |
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| 211 | |
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| 212 | #ifndef ASM |
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| 213 | |
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| 214 | /** |
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| 215 | * @brief Set of Per CPU Core Information |
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| 216 | * |
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| 217 | * This is an array of per CPU core information. |
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| 218 | */ |
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[3f764a8] | 219 | extern Per_CPU_Control _Per_CPU_Information[] CPU_STRUCTURE_ALIGNMENT; |
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[06dcaf0] | 220 | |
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| 221 | #if defined(RTEMS_SMP) |
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| 222 | /** |
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| 223 | * @brief Set of Pointers to Per CPU Core Information |
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| 224 | * |
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| 225 | * This is an array of pointers to each CPU's per CPU data structure. |
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| 226 | * It should be simpler to retrieve this pointer in assembly language |
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| 227 | * that to calculate the array offset. |
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| 228 | */ |
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| 229 | extern Per_CPU_Control *_Per_CPU_Information_p[]; |
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| 230 | |
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| 231 | /** |
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| 232 | * @brief Initialize SMP Handler |
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| 233 | * |
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| 234 | * This method initialize the SMP Handler. |
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| 235 | */ |
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| 236 | void _SMP_Handler_initialize(void); |
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| 237 | |
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| 238 | /** |
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| 239 | * @brief Allocate and Initialize Per CPU Structures |
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| 240 | * |
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| 241 | * This method allocates and initialize the per CPU structure. |
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| 242 | */ |
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| 243 | void _Per_CPU_Initialize(void); |
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| 244 | |
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| 245 | #endif |
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[11e8bc5] | 246 | |
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| 247 | /* |
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[06dcaf0] | 248 | * On a non SMP system, the bsp_smp_processor_id is defined to 0. |
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[11e8bc5] | 249 | * Thus when built for non-SMP, there should be no performance penalty. |
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| 250 | */ |
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[06dcaf0] | 251 | #define _Thread_Heir \ |
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| 252 | _Per_CPU_Information[bsp_smp_processor_id()].heir |
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| 253 | #define _Thread_Executing \ |
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| 254 | _Per_CPU_Information[bsp_smp_processor_id()].executing |
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| 255 | #define _Thread_Idle \ |
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| 256 | _Per_CPU_Information[bsp_smp_processor_id()].idle |
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| 257 | #define _ISR_Nest_level \ |
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| 258 | _Per_CPU_Information[bsp_smp_processor_id()].isr_nest_level |
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| 259 | #define _CPU_Interrupt_stack_low \ |
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| 260 | _Per_CPU_Information[bsp_smp_processor_id()].interrupt_stack_low |
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| 261 | #define _CPU_Interrupt_stack_high \ |
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| 262 | _Per_CPU_Information[bsp_smp_processor_id()].interrupt_stack_high |
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| 263 | #define _Thread_Dispatch_necessary \ |
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| 264 | _Per_CPU_Information[bsp_smp_processor_id()].dispatch_necessary |
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[0a101d57] | 265 | #ifndef __RTEMS_USE_TICKS_FOR_STATISTICS__ |
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| 266 | #define _Thread_Time_of_last_context_switch \ |
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| 267 | _Per_CPU_Information[bsp_smp_processor_id()].time_of_last_context_switch |
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| 268 | #endif |
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| 269 | |
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[11e8bc5] | 270 | |
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| 271 | #endif /* ASM */ |
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| 272 | |
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| 273 | #ifdef __cplusplus |
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| 274 | } |
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| 275 | #endif |
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| 276 | |
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| 277 | /**@}*/ |
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| 278 | |
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| 279 | #endif |
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| 280 | /* end of include file */ |
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