[2d915cf] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup ScoreISRLocks |
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| 5 | * |
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| 6 | * @brief ISR Locks |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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| 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Dornierstr. 4 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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[c499856] | 20 | * http://www.rtems.org/license/LICENSE. |
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[2d915cf] | 21 | */ |
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| 22 | |
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| 23 | #ifndef _RTEMS_SCORE_ISR_LOCK_H |
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| 24 | #define _RTEMS_SCORE_ISR_LOCK_H |
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| 25 | |
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| 26 | #include <rtems/score/isrlevel.h> |
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| 27 | #include <rtems/score/smplock.h> |
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| 28 | |
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| 29 | #ifdef __cplusplus |
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| 30 | extern "C" { |
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| 31 | #endif |
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| 32 | |
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| 33 | /** |
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| 34 | * @defgroup ScoreISRLocks ISR Locks |
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| 35 | * |
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| 36 | * @ingroup ScoreISR |
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| 37 | * |
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| 38 | * @brief Low-level lock to protect critical sections accessed by threads and |
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| 39 | * interrupt service routines. |
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| 40 | * |
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| 41 | * On single processor configurations the ISR locks degrade to simple ISR |
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| 42 | * disable/enable sequences. No additional storage or objects are required. |
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| 43 | * |
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| 44 | * This synchronization primitive is supported on SMP configurations. Here SMP |
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| 45 | * locks are used. |
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| 46 | * |
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| 47 | * @{ |
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| 48 | */ |
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| 49 | |
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| 50 | /** |
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| 51 | * @brief ISR lock control. |
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| 52 | */ |
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| 53 | typedef struct { |
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[d50acdbb] | 54 | #if defined( RTEMS_SMP ) |
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| 55 | SMP_lock_Control lock; |
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| 56 | #endif |
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[2d915cf] | 57 | } ISR_lock_Control; |
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| 58 | |
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[d50acdbb] | 59 | /** |
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| 60 | * @brief Local ISR lock context for acquire and release pairs. |
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| 61 | */ |
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| 62 | typedef struct { |
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| 63 | #if defined( RTEMS_SMP ) |
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| 64 | SMP_lock_Context lock_context; |
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| 65 | #else |
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| 66 | ISR_Level isr_level; |
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| 67 | #endif |
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| 68 | } ISR_lock_Context; |
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| 69 | |
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[2d915cf] | 70 | /** |
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| 71 | * @brief Initializer for static initialization of ISR locks. |
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| 72 | */ |
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| 73 | #if defined( RTEMS_SMP ) |
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[53ad908] | 74 | #define ISR_LOCK_INITIALIZER( name ) \ |
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| 75 | { SMP_LOCK_INITIALIZER( name ) } |
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[2d915cf] | 76 | #else |
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[53ad908] | 77 | #define ISR_LOCK_INITIALIZER( name ) \ |
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[2d915cf] | 78 | { } |
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| 79 | #endif |
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| 80 | |
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| 81 | /** |
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| 82 | * @brief Initializes an ISR lock. |
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| 83 | * |
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| 84 | * Concurrent initialization leads to unpredictable results. |
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| 85 | * |
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[d50acdbb] | 86 | * @param[in,out] lock The ISR lock control. |
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[53ad908] | 87 | * @param[in] name The name for the ISR lock. This name must be persistent |
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| 88 | * throughout the life time of this lock. |
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[2d915cf] | 89 | */ |
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[53ad908] | 90 | static inline void _ISR_lock_Initialize( |
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| 91 | ISR_lock_Control *lock, |
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| 92 | const char *name |
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| 93 | ) |
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[d50acdbb] | 94 | { |
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[2d915cf] | 95 | #if defined( RTEMS_SMP ) |
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[53ad908] | 96 | _SMP_lock_Initialize( &lock->lock, name ); |
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[2d915cf] | 97 | #else |
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[d50acdbb] | 98 | (void) lock; |
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[53ad908] | 99 | (void) name; |
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[2d915cf] | 100 | #endif |
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[d50acdbb] | 101 | } |
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[2d915cf] | 102 | |
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[28779c7] | 103 | /** |
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| 104 | * @brief Destroys an ISR lock. |
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| 105 | * |
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| 106 | * Concurrent destruction leads to unpredictable results. |
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| 107 | * |
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| 108 | * @param[in,out] lock The ISR lock control. |
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| 109 | */ |
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| 110 | static inline void _ISR_lock_Destroy( ISR_lock_Control *lock ) |
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| 111 | { |
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| 112 | #if defined( RTEMS_SMP ) |
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| 113 | _SMP_lock_Destroy( &lock->lock ); |
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| 114 | #else |
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| 115 | (void) lock; |
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| 116 | #endif |
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| 117 | } |
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| 118 | |
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[2d915cf] | 119 | /** |
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| 120 | * @brief Acquires an ISR lock. |
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| 121 | * |
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| 122 | * Interrupts will be disabled. On SMP configurations this function acquires |
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| 123 | * an SMP lock. |
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| 124 | * |
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| 125 | * This function can be used in thread and interrupt context. |
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| 126 | * |
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[d50acdbb] | 127 | * @param[in,out] lock The ISR lock control. |
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| 128 | * @param[in,out] context The local ISR lock context for an acquire and release |
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| 129 | * pair. |
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[2d915cf] | 130 | * |
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[8d640134] | 131 | * @see _ISR_lock_Release_and_ISR_enable(). |
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[2d915cf] | 132 | */ |
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[d50acdbb] | 133 | static inline void _ISR_lock_ISR_disable_and_acquire( |
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| 134 | ISR_lock_Control *lock, |
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| 135 | ISR_lock_Context *context |
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| 136 | ) |
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| 137 | { |
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[2d915cf] | 138 | #if defined( RTEMS_SMP ) |
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[d50acdbb] | 139 | _SMP_lock_ISR_disable_and_acquire( &lock->lock, &context->lock_context ); |
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[2d915cf] | 140 | #else |
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[d50acdbb] | 141 | (void) lock; |
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| 142 | _ISR_Disable( context->isr_level ); |
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[2d915cf] | 143 | #endif |
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[d50acdbb] | 144 | } |
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[2d915cf] | 145 | |
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| 146 | /** |
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| 147 | * @brief Releases an ISR lock. |
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| 148 | * |
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| 149 | * The interrupt status will be restored. On SMP configurations this function |
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| 150 | * releases an SMP lock. |
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| 151 | * |
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| 152 | * This function can be used in thread and interrupt context. |
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| 153 | * |
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[d50acdbb] | 154 | * @param[in,out] lock The ISR lock control. |
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| 155 | * @param[in,out] context The local ISR lock context for an acquire and release |
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| 156 | * pair. |
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[2d915cf] | 157 | * |
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[8d640134] | 158 | * @see _ISR_lock_ISR_disable_and_acquire(). |
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[2d915cf] | 159 | */ |
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[d50acdbb] | 160 | static inline void _ISR_lock_Release_and_ISR_enable( |
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| 161 | ISR_lock_Control *lock, |
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| 162 | ISR_lock_Context *context |
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| 163 | ) |
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| 164 | { |
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[2d915cf] | 165 | #if defined( RTEMS_SMP ) |
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[d50acdbb] | 166 | _SMP_lock_Release_and_ISR_enable( &lock->lock, &context->lock_context ); |
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[2d915cf] | 167 | #else |
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[d50acdbb] | 168 | (void) lock; |
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| 169 | _ISR_Enable( context->isr_level ); |
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[2d915cf] | 170 | #endif |
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[d50acdbb] | 171 | } |
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[2d915cf] | 172 | |
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[8d640134] | 173 | /** |
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| 174 | * @brief Acquires an ISR lock inside an ISR disabled section. |
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| 175 | * |
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| 176 | * The interrupt status will remain unchanged. On SMP configurations this |
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| 177 | * function acquires an SMP lock. |
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| 178 | * |
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| 179 | * In case the executing context can be interrupted by higher priority |
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| 180 | * interrupts and these interrupts enter the critical section protected by this |
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| 181 | * lock, then the result is unpredictable. |
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| 182 | * |
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[d50acdbb] | 183 | * @param[in,out] lock The ISR lock control. |
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| 184 | * @param[in,out] context The local ISR lock context for an acquire and release |
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| 185 | * pair. |
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[8d640134] | 186 | * |
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| 187 | * @see _ISR_lock_Release(). |
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| 188 | */ |
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[d50acdbb] | 189 | static inline void _ISR_lock_Acquire( |
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| 190 | ISR_lock_Control *lock, |
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| 191 | ISR_lock_Context *context |
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| 192 | ) |
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| 193 | { |
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[8d640134] | 194 | #if defined( RTEMS_SMP ) |
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[d50acdbb] | 195 | _SMP_lock_Acquire( &lock->lock, &context->lock_context ); |
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[8d640134] | 196 | #else |
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[d50acdbb] | 197 | (void) lock; |
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| 198 | (void) context; |
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[8d640134] | 199 | #endif |
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[d50acdbb] | 200 | } |
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[8d640134] | 201 | |
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| 202 | /** |
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| 203 | * @brief Releases an ISR lock inside an ISR disabled section. |
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| 204 | * |
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| 205 | * The interrupt status will remain unchanged. On SMP configurations this |
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| 206 | * function releases an SMP lock. |
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| 207 | * |
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[d50acdbb] | 208 | * @param[in,out] lock The ISR lock control. |
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| 209 | * @param[in,out] context The local ISR lock context for an acquire and release |
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| 210 | * pair. |
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[8d640134] | 211 | * |
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| 212 | * @see _ISR_lock_Acquire(). |
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| 213 | */ |
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[d50acdbb] | 214 | static inline void _ISR_lock_Release( |
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| 215 | ISR_lock_Control *lock, |
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| 216 | ISR_lock_Context *context |
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| 217 | ) |
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| 218 | { |
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[8d640134] | 219 | #if defined( RTEMS_SMP ) |
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[d50acdbb] | 220 | _SMP_lock_Release( &lock->lock, &context->lock_context ); |
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[8d640134] | 221 | #else |
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[d50acdbb] | 222 | (void) lock; |
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| 223 | (void) context; |
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[8d640134] | 224 | #endif |
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[d50acdbb] | 225 | } |
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[8d640134] | 226 | |
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[2d915cf] | 227 | /** @} */ |
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| 228 | |
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| 229 | #ifdef __cplusplus |
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| 230 | } |
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| 231 | #endif |
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| 232 | |
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| 233 | #endif /* _RTEMS_SCORE_ISR_LOCK_H */ |
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