[2d915cf] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup ScoreISRLocks |
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| 5 | * |
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| 6 | * @brief ISR Locks |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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| 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Dornierstr. 4 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.rtems.com/license/LICENSE. |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef _RTEMS_SCORE_ISR_LOCK_H |
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| 24 | #define _RTEMS_SCORE_ISR_LOCK_H |
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| 25 | |
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| 26 | #include <rtems/score/isrlevel.h> |
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| 27 | #include <rtems/score/smplock.h> |
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| 28 | |
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| 29 | #ifdef __cplusplus |
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| 30 | extern "C" { |
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| 31 | #endif |
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| 32 | |
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| 33 | /** |
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| 34 | * @defgroup ScoreISRLocks ISR Locks |
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| 35 | * |
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| 36 | * @ingroup ScoreISR |
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| 37 | * |
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| 38 | * @brief Low-level lock to protect critical sections accessed by threads and |
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| 39 | * interrupt service routines. |
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| 40 | * |
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| 41 | * On single processor configurations the ISR locks degrade to simple ISR |
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| 42 | * disable/enable sequences. No additional storage or objects are required. |
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| 43 | * |
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| 44 | * This synchronization primitive is supported on SMP configurations. Here SMP |
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| 45 | * locks are used. |
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| 46 | * |
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| 47 | * @{ |
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| 48 | */ |
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| 49 | |
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| 50 | /** |
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| 51 | * @brief ISR lock control. |
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| 52 | */ |
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| 53 | typedef struct { |
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[d50acdbb] | 54 | #if defined( RTEMS_SMP ) |
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| 55 | SMP_lock_Control lock; |
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| 56 | #endif |
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[2d915cf] | 57 | } ISR_lock_Control; |
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| 58 | |
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[d50acdbb] | 59 | /** |
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| 60 | * @brief Local ISR lock context for acquire and release pairs. |
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| 61 | */ |
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| 62 | typedef struct { |
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| 63 | #if defined( RTEMS_SMP ) |
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| 64 | SMP_lock_Context lock_context; |
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| 65 | #else |
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| 66 | ISR_Level isr_level; |
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| 67 | #endif |
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| 68 | } ISR_lock_Context; |
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| 69 | |
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[2d915cf] | 70 | /** |
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| 71 | * @brief Initializer for static initialization of ISR locks. |
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| 72 | */ |
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| 73 | #if defined( RTEMS_SMP ) |
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| 74 | #define ISR_LOCK_INITIALIZER \ |
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| 75 | { SMP_LOCK_INITIALIZER } |
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| 76 | #else |
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| 77 | #define ISR_LOCK_INITIALIZER \ |
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| 78 | { } |
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| 79 | #endif |
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| 80 | |
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| 81 | /** |
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| 82 | * @brief Initializes an ISR lock. |
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| 83 | * |
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| 84 | * Concurrent initialization leads to unpredictable results. |
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| 85 | * |
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[d50acdbb] | 86 | * @param[in,out] lock The ISR lock control. |
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[2d915cf] | 87 | */ |
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[d50acdbb] | 88 | static inline void _ISR_lock_Initialize( ISR_lock_Control *lock ) |
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| 89 | { |
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[2d915cf] | 90 | #if defined( RTEMS_SMP ) |
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[d50acdbb] | 91 | _SMP_lock_Initialize( &lock->lock ); |
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[2d915cf] | 92 | #else |
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[d50acdbb] | 93 | (void) lock; |
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[2d915cf] | 94 | #endif |
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[d50acdbb] | 95 | } |
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[2d915cf] | 96 | |
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[28779c7] | 97 | /** |
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| 98 | * @brief Destroys an ISR lock. |
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| 99 | * |
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| 100 | * Concurrent destruction leads to unpredictable results. |
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| 101 | * |
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| 102 | * @param[in,out] lock The ISR lock control. |
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| 103 | */ |
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| 104 | static inline void _ISR_lock_Destroy( ISR_lock_Control *lock ) |
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| 105 | { |
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| 106 | #if defined( RTEMS_SMP ) |
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| 107 | _SMP_lock_Destroy( &lock->lock ); |
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| 108 | #else |
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| 109 | (void) lock; |
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| 110 | #endif |
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| 111 | } |
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| 112 | |
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[2d915cf] | 113 | /** |
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| 114 | * @brief Acquires an ISR lock. |
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| 115 | * |
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| 116 | * Interrupts will be disabled. On SMP configurations this function acquires |
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| 117 | * an SMP lock. |
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| 118 | * |
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| 119 | * This function can be used in thread and interrupt context. |
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| 120 | * |
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[d50acdbb] | 121 | * @param[in,out] lock The ISR lock control. |
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| 122 | * @param[in,out] context The local ISR lock context for an acquire and release |
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| 123 | * pair. |
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[2d915cf] | 124 | * |
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[8d640134] | 125 | * @see _ISR_lock_Release_and_ISR_enable(). |
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[2d915cf] | 126 | */ |
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[d50acdbb] | 127 | static inline void _ISR_lock_ISR_disable_and_acquire( |
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| 128 | ISR_lock_Control *lock, |
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| 129 | ISR_lock_Context *context |
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| 130 | ) |
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| 131 | { |
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[2d915cf] | 132 | #if defined( RTEMS_SMP ) |
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[d50acdbb] | 133 | _SMP_lock_ISR_disable_and_acquire( &lock->lock, &context->lock_context ); |
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[2d915cf] | 134 | #else |
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[d50acdbb] | 135 | (void) lock; |
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| 136 | _ISR_Disable( context->isr_level ); |
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[2d915cf] | 137 | #endif |
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[d50acdbb] | 138 | } |
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[2d915cf] | 139 | |
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| 140 | /** |
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| 141 | * @brief Releases an ISR lock. |
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| 142 | * |
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| 143 | * The interrupt status will be restored. On SMP configurations this function |
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| 144 | * releases an SMP lock. |
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| 145 | * |
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| 146 | * This function can be used in thread and interrupt context. |
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| 147 | * |
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[d50acdbb] | 148 | * @param[in,out] lock The ISR lock control. |
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| 149 | * @param[in,out] context The local ISR lock context for an acquire and release |
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| 150 | * pair. |
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[2d915cf] | 151 | * |
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[8d640134] | 152 | * @see _ISR_lock_ISR_disable_and_acquire(). |
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[2d915cf] | 153 | */ |
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[d50acdbb] | 154 | static inline void _ISR_lock_Release_and_ISR_enable( |
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| 155 | ISR_lock_Control *lock, |
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| 156 | ISR_lock_Context *context |
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| 157 | ) |
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| 158 | { |
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[2d915cf] | 159 | #if defined( RTEMS_SMP ) |
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[d50acdbb] | 160 | _SMP_lock_Release_and_ISR_enable( &lock->lock, &context->lock_context ); |
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[2d915cf] | 161 | #else |
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[d50acdbb] | 162 | (void) lock; |
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| 163 | _ISR_Enable( context->isr_level ); |
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[2d915cf] | 164 | #endif |
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[d50acdbb] | 165 | } |
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[2d915cf] | 166 | |
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[8d640134] | 167 | /** |
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| 168 | * @brief Acquires an ISR lock inside an ISR disabled section. |
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| 169 | * |
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| 170 | * The interrupt status will remain unchanged. On SMP configurations this |
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| 171 | * function acquires an SMP lock. |
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| 172 | * |
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| 173 | * In case the executing context can be interrupted by higher priority |
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| 174 | * interrupts and these interrupts enter the critical section protected by this |
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| 175 | * lock, then the result is unpredictable. |
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| 176 | * |
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[d50acdbb] | 177 | * @param[in,out] lock The ISR lock control. |
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| 178 | * @param[in,out] context The local ISR lock context for an acquire and release |
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| 179 | * pair. |
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[8d640134] | 180 | * |
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| 181 | * @see _ISR_lock_Release(). |
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| 182 | */ |
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[d50acdbb] | 183 | static inline void _ISR_lock_Acquire( |
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| 184 | ISR_lock_Control *lock, |
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| 185 | ISR_lock_Context *context |
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| 186 | ) |
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| 187 | { |
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[8d640134] | 188 | #if defined( RTEMS_SMP ) |
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[d50acdbb] | 189 | _SMP_lock_Acquire( &lock->lock, &context->lock_context ); |
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[8d640134] | 190 | #else |
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[d50acdbb] | 191 | (void) lock; |
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| 192 | (void) context; |
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[8d640134] | 193 | #endif |
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[d50acdbb] | 194 | } |
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[8d640134] | 195 | |
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| 196 | /** |
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| 197 | * @brief Releases an ISR lock inside an ISR disabled section. |
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| 198 | * |
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| 199 | * The interrupt status will remain unchanged. On SMP configurations this |
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| 200 | * function releases an SMP lock. |
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| 201 | * |
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[d50acdbb] | 202 | * @param[in,out] lock The ISR lock control. |
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| 203 | * @param[in,out] context The local ISR lock context for an acquire and release |
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| 204 | * pair. |
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[8d640134] | 205 | * |
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| 206 | * @see _ISR_lock_Acquire(). |
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| 207 | */ |
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[d50acdbb] | 208 | static inline void _ISR_lock_Release( |
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| 209 | ISR_lock_Control *lock, |
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| 210 | ISR_lock_Context *context |
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| 211 | ) |
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| 212 | { |
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[8d640134] | 213 | #if defined( RTEMS_SMP ) |
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[d50acdbb] | 214 | _SMP_lock_Release( &lock->lock, &context->lock_context ); |
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[8d640134] | 215 | #else |
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[d50acdbb] | 216 | (void) lock; |
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| 217 | (void) context; |
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[8d640134] | 218 | #endif |
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[d50acdbb] | 219 | } |
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[8d640134] | 220 | |
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[2d915cf] | 221 | /** @} */ |
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| 222 | |
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| 223 | #ifdef __cplusplus |
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| 224 | } |
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| 225 | #endif |
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| 226 | |
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| 227 | #endif /* _RTEMS_SCORE_ISR_LOCK_H */ |
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