1 | /** |
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2 | * @file rtems/score/isrlevel.h |
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3 | * |
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4 | * @brief ISR Level Type |
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5 | * |
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6 | * This include file defines the ISR Level type. It exists to |
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7 | * simplify include dependencies. It is part of the ISR Handler. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * COPYRIGHT (c) 1989-2011. |
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12 | * On-Line Applications Research Corporation (OAR). |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.org/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #ifndef _RTEMS_SCORE_ISR_LEVEL_h |
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20 | #define _RTEMS_SCORE_ISR_LEVEL_h |
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21 | |
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22 | #include <rtems/score/cpu.h> |
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23 | #include <rtems/score/assert.h> |
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24 | |
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25 | #ifdef __cplusplus |
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26 | extern "C" { |
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27 | #endif |
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28 | |
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29 | /** |
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30 | * @defgroup ScoreISR ISR Handler |
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31 | * |
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32 | * @ingroup Score |
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33 | * |
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34 | * @addtogroup ScoreISR ISR Handler |
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35 | */ |
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36 | /**@{*/ |
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37 | |
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38 | /** |
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39 | * The following type defines the control block used to manage |
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40 | * the interrupt level portion of the status register. |
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41 | */ |
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42 | typedef uint32_t ISR_Level; |
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43 | |
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44 | /** |
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45 | * @brief Disables interrupts on this processor. |
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46 | * |
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47 | * This macro disables all interrupts on this processor so that a critical |
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48 | * section of code is protected from concurrent access by interrupts of this |
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49 | * processor. Disabling of interrupts disables thread dispatching on the |
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50 | * processor as well. |
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51 | * |
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52 | * On SMP configurations other processors can enter such sections if not |
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53 | * protected by other means. |
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54 | * |
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55 | * @param[out] _level The argument @a _level will contain the previous |
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56 | * interrupt mask level. |
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57 | */ |
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58 | #define _ISR_Disable( _level ) \ |
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59 | do { \ |
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60 | _CPU_ISR_Disable( _level ); \ |
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61 | _Assert( _Debug_Is_owner_of_giant() ); \ |
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62 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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63 | } while (0) |
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64 | |
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65 | /** |
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66 | * @brief Enables interrupts on this processor. |
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67 | * |
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68 | * This macro restores the interrupt status on the processor with the |
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69 | * interrupt level value obtained by _ISR_Disable(). It is used at the end of |
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70 | * a critical section of code to enable interrupts so they can be processed |
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71 | * again. |
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72 | * |
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73 | * @param[in] _level The interrupt level previously obtained by |
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74 | * _ISR_Disable(). |
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75 | */ |
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76 | #define _ISR_Enable( _level ) \ |
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77 | do { \ |
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78 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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79 | _Assert( _Debug_Is_owner_of_giant() ); \ |
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80 | _CPU_ISR_Enable( _level ); \ |
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81 | } while (0) |
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82 | |
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83 | /** |
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84 | * @brief Temporarily enables interrupts on this processor. |
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85 | * |
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86 | * This macro temporarily enables interrupts to the previous |
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87 | * interrupt mask level and then disables all interrupts so that |
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88 | * the caller can continue into the second part of a critical |
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89 | * section. |
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90 | * |
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91 | * This routine is used to temporarily enable interrupts |
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92 | * during a long critical section. It is used in long sections of |
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93 | * critical code when a point is reached at which interrupts can |
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94 | * be temporarily enabled. Deciding where to flash interrupts |
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95 | * in a long critical section is often difficult and the point |
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96 | * must be selected with care to ensure that the critical section |
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97 | * properly protects itself. |
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98 | * |
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99 | * @param[in] _level The interrupt level previously obtained by |
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100 | * _ISR_Disable(). |
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101 | */ |
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102 | #define _ISR_Flash( _level ) \ |
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103 | do { \ |
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104 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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105 | _Assert( _Debug_Is_owner_of_giant() ); \ |
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106 | _CPU_ISR_Flash( _level ); \ |
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107 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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108 | } while (0) |
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109 | |
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110 | /** |
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111 | * @brief Return current interrupt level. |
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112 | * |
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113 | * This routine returns the current interrupt level. |
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114 | * |
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115 | * LM32 Specific Information: |
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116 | * XXX document implementation including references if appropriate |
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117 | * |
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118 | * @retval This method returns the current level. |
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119 | */ |
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120 | #define _ISR_Get_level() \ |
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121 | _CPU_ISR_Get_level() |
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122 | |
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123 | /** |
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124 | * @brief Set current interrupt level. |
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125 | * |
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126 | * This routine sets the current interrupt level to that specified |
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127 | * by @a _new_level. The new interrupt level is effective when the |
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128 | * routine exits. |
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129 | * |
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130 | * @param[in] _new_level contains the desired interrupt level. |
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131 | */ |
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132 | #define _ISR_Set_level( _new_level ) \ |
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133 | do { \ |
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134 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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135 | _CPU_ISR_Set_level( _new_level ); \ |
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136 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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137 | } while (0) |
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138 | |
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139 | #define _ISR_Disable_without_giant( _level ) \ |
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140 | do { \ |
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141 | _CPU_ISR_Disable( _level ); \ |
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142 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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143 | } while (0) |
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144 | |
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145 | #define _ISR_Enable_without_giant( _level ) \ |
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146 | do { \ |
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147 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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148 | _CPU_ISR_Enable( _level ); \ |
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149 | } while (0) |
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150 | |
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151 | /**@}*/ |
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152 | |
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153 | #ifdef __cplusplus |
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154 | } |
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155 | #endif |
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156 | #endif |
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