source: rtems/cpukit/score/include/rtems/score/isrlevel.h @ 7e119990

4.115
Last change on this file since 7e119990 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

Change all references of rtems.com to rtems.org.

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/**
2 *  @file  rtems/score/isrlevel.h
3 *
4 *  @brief ISR Level Type
5 *
6 *  This include file defines the ISR Level type.  It exists to
7 *  simplify include dependencies.  It is part of the ISR Handler.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_ISR_LEVEL_h
20#define _RTEMS_SCORE_ISR_LEVEL_h
21
22#include <rtems/score/cpu.h>
23#include <rtems/score/assert.h>
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29/**
30 *  @defgroup ScoreISR ISR Handler
31 *
32 *  @ingroup Score
33 *
34 *  @addtogroup ScoreISR ISR Handler
35 */
36/**@{*/
37
38/**
39 *  The following type defines the control block used to manage
40 *  the interrupt level portion of the status register.
41 */
42typedef uint32_t   ISR_Level;
43
44/**
45 *  @brief Disables interrupts on this processor.
46 *
47 *  This macro disables all interrupts on this processor so that a critical
48 *  section of code is protected from concurrent access by interrupts of this
49 *  processor.  Disabling of interrupts disables thread dispatching on the
50 *  processor as well.
51 *
52 *  On SMP configurations other processors can enter such sections if not
53 *  protected by other means.
54 *
55 *  @param[out] _level The argument @a _level will contain the previous
56 *  interrupt mask level.
57 */
58#define _ISR_Disable( _level ) \
59  do { \
60    _CPU_ISR_Disable( _level ); \
61    _Assert( _Debug_Is_owner_of_giant() ); \
62    RTEMS_COMPILER_MEMORY_BARRIER(); \
63  } while (0)
64
65/**
66 *  @brief Enables interrupts on this processor.
67 *
68 *  This macro restores the interrupt status on the processor with the
69 *  interrupt level value obtained by _ISR_Disable().  It is used at the end of
70 *  a critical section of code to enable interrupts so they can be processed
71 *  again.
72 *
73 *  @param[in] _level The interrupt level previously obtained by
74 *  _ISR_Disable().
75 */
76#define _ISR_Enable( _level ) \
77  do { \
78    RTEMS_COMPILER_MEMORY_BARRIER(); \
79    _Assert( _Debug_Is_owner_of_giant() ); \
80    _CPU_ISR_Enable( _level ); \
81  } while (0)
82
83/**
84 *  @brief Temporarily enables interrupts on this processor.
85 *
86 *  This macro temporarily enables interrupts to the previous
87 *  interrupt mask level and then disables all interrupts so that
88 *  the caller can continue into the second part of a critical
89 *  section.
90 *
91 *  This routine is used to temporarily enable interrupts
92 *  during a long critical section.  It is used in long sections of
93 *  critical code when a point is reached at which interrupts can
94 *  be temporarily enabled.  Deciding where to flash interrupts
95 *  in a long critical section is often difficult and the point
96 *  must be selected with care to ensure that the critical section
97 *  properly protects itself.
98 *
99 *  @param[in] _level The interrupt level previously obtained by
100 *  _ISR_Disable().
101 */
102#define _ISR_Flash( _level ) \
103  do { \
104    RTEMS_COMPILER_MEMORY_BARRIER(); \
105    _Assert( _Debug_Is_owner_of_giant() ); \
106    _CPU_ISR_Flash( _level ); \
107    RTEMS_COMPILER_MEMORY_BARRIER(); \
108  } while (0)
109
110/**
111 *  @brief Return current interrupt level.
112 *
113 *  This routine returns the current interrupt level.
114 *
115 *  LM32 Specific Information:
116 *  XXX document implementation including references if appropriate
117 *
118 *  @retval This method returns the current level.
119 */
120#define _ISR_Get_level() \
121        _CPU_ISR_Get_level()
122
123/**
124 *  @brief Set current interrupt level.
125 *
126 *  This routine sets the current interrupt level to that specified
127 *  by @a _new_level.  The new interrupt level is effective when the
128 *  routine exits.
129 *
130 *  @param[in] _new_level contains the desired interrupt level.
131 */
132#define _ISR_Set_level( _new_level ) \
133  do { \
134    RTEMS_COMPILER_MEMORY_BARRIER();  \
135    _CPU_ISR_Set_level( _new_level ); \
136    RTEMS_COMPILER_MEMORY_BARRIER();  \
137  } while (0)
138
139#define _ISR_Disable_without_giant( _level ) \
140  do { \
141    _CPU_ISR_Disable( _level ); \
142    RTEMS_COMPILER_MEMORY_BARRIER(); \
143  } while (0)
144
145#define _ISR_Enable_without_giant( _level ) \
146  do { \
147    RTEMS_COMPILER_MEMORY_BARRIER(); \
148    _CPU_ISR_Enable( _level ); \
149  } while (0)
150
151/**@}*/
152
153#ifdef __cplusplus
154}
155#endif
156#endif
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