source: rtems/cpukit/score/include/rtems/score/isr.h @ df00777

4.115
Last change on this file since df00777 was df00777, checked in by Jennifer Averett <Jennifer.Averett@…>, on Jul 15, 2011 at 2:36:37 PM

2011-07-15 Jennifer Averett <Jennifer.Averett@…>

  • score/Makefile.am, score/preinstall.am, score/include/rtems/score/isr.h, score/include/rtems/score/percpu.h: Split isrlevel into its own file to avoid a circular dependancy in smp code.
  • score/include/rtems/score/isrlevel.h: New file.
  • Property mode set to 100644
File size: 6.1 KB
Line 
1/**
2 *  @file  rtems/score/isr.h
3 *
4 *  This include file contains all the constants and structures associated
5 *  with the management of processor interrupt levels.  This handler
6 *  supports interrupt critical sections, vectoring of user interrupt
7 *  handlers, nesting of interrupts, and manipulating interrupt levels.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2006.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *  $Id$
19 */
20
21#ifndef _RTEMS_SCORE_ISR_H
22#define _RTEMS_SCORE_ISR_H
23
24#include <rtems/score/percpu.h>
25
26/**
27 *  @defgroup ScoreISR ISR Handler
28 *
29 *  @ingroup Score
30 *
31 *  This handler encapsulates functionality which provides the foundation
32 *  ISR services used in all of the APIs supported by RTEMS.
33 *
34 *  The ISR Nest level counter variable is maintained as part of the
35 *  per cpu data structure.
36 */
37/**@{*/
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43/**
44 *  The following type defines the type used to manage the vectors.
45 */
46typedef uint32_t   ISR_Vector_number;
47
48/**
49 *  Return type for ISR Handler
50 */
51typedef void ISR_Handler;
52
53/**
54 *  Pointer to an ISR Handler
55 */
56#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
57typedef ISR_Handler ( *ISR_Handler_entry )(
58                 ISR_Vector_number,
59                 CPU_Interrupt_frame *
60             );
61#else
62typedef ISR_Handler ( *ISR_Handler_entry )(
63                 ISR_Vector_number
64             );
65#endif
66
67/**
68 *  This constant promotes out the number of vectors truly supported by
69 *  the current CPU being used.  This is usually the number of distinct vectors
70 *  the cpu can vector.
71 */
72#define ISR_NUMBER_OF_VECTORS                CPU_INTERRUPT_NUMBER_OF_VECTORS
73
74/**
75 *  This constant promotes out the highest valid interrupt vector number.
76 */
77#define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER  CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER
78
79#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
80/**
81 *  The following declares the Vector Table.  Application
82 *  interrupt service routines are vectored by the ISR Handler via this table.
83 */
84SCORE_EXTERN ISR_Handler_entry *_ISR_Vector_table;
85#endif
86
87/**
88 *  This routine performs the initialization necessary for this handler.
89 */
90void _ISR_Handler_initialization ( void );
91
92/**
93 *  This routine disables all interrupts so that a critical section
94 *  of code can be executing without being interrupted.  Upon return,
95 *  the argument _level will contain the previous interrupt mask level.
96 */
97#define _ISR_Disable( _level ) \
98  do { \
99    _CPU_ISR_Disable( _level ); \
100    RTEMS_COMPILER_MEMORY_BARRIER(); \
101  } while (0)
102
103/**
104 *  This routine enables interrupts to the previous interrupt mask
105 *  LEVEL.  It is used at the end of a critical section of code to
106 *  enable interrupts so they can be processed again.
107 */
108#define _ISR_Enable( _level ) \
109  do { \
110    RTEMS_COMPILER_MEMORY_BARRIER(); \
111    _CPU_ISR_Enable( _level ); \
112  } while (0)
113
114/**
115 *  This routine temporarily enables interrupts to the previous
116 *  interrupt mask level and then disables all interrupts so that
117 *  the caller can continue into the second part of a critical
118 *  section.  This routine is used to temporarily enable interrupts
119 *  during a long critical section.  It is used in long sections of
120 *  critical code when a point is reached at which interrupts can
121 *  be temporarily enabled.  Deciding where to flash interrupts
122 *  in a long critical section is often difficult and the point
123 *  must be selected with care to ensure that the critical section
124 *  properly protects itself.
125 */
126#define _ISR_Flash( _level ) \
127  do { \
128    RTEMS_COMPILER_MEMORY_BARRIER(); \
129    _CPU_ISR_Flash( _level ); \
130    RTEMS_COMPILER_MEMORY_BARRIER(); \
131  } while (0)
132
133/**
134 *  This routine installs new_handler as the interrupt service routine
135 *  for the specified vector.  The previous interrupt service routine is
136 *  returned as old_handler.
137 */
138#define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \
139  _CPU_ISR_install_vector( _vector, _new_handler, _old_handler )
140
141/**
142 *  This routine returns the current interrupt level.
143 */
144#define _ISR_Get_level() \
145        _CPU_ISR_Get_level()
146
147/**
148 *  This routine sets the current interrupt level to that specified
149 *  by new_level.  The new interrupt level is effective when the
150 *  routine exits.
151 */
152#define _ISR_Set_level( _new_level ) \
153  do { \
154    RTEMS_COMPILER_MEMORY_BARRIER();  \
155    _CPU_ISR_Set_level( _new_level ); \
156    RTEMS_COMPILER_MEMORY_BARRIER();  \
157    } while (0)
158
159
160/**
161 *  This routine is the interrupt dispatcher.  ALL interrupts
162 *  are vectored to this routine so that minimal context can be saved
163 *  and setup performed before the application's high-level language
164 *  interrupt service routine is invoked.   After the application's
165 *  interrupt service routine returns control to this routine, it
166 *  will determine if a thread dispatch is necessary.  If so, it will
167 *  ensure that the necessary thread scheduling operations are
168 *  performed when the outermost interrupt service routine exits.
169 *
170 *  @note  Implemented in assembly language.
171 */
172void _ISR_Handler( void );
173
174/**
175 *  This routine provides a wrapper so that the routine
176 *  @ref _Thread_Dispatch can be invoked when a reschedule is necessary
177 *  at the end of the outermost interrupt service routine.  This
178 *  wrapper is necessary to establish the processor context needed
179 *  by _Thread_Dispatch and to save the processor context which is
180 *  corrupted by _Thread_Dispatch.  This context typically consists
181 *  of registers which are not preserved across routine invocations.
182 *
183 *  @note  Implemented in assembly language.
184 */
185void _ISR_Dispatch( void );
186
187/**
188 *  This function returns true if the processor is currently servicing
189 *  and interrupt and false otherwise.   A return value of true indicates
190 *  that the caller is an interrupt service routine, NOT a thread.  The
191 */
192#if (CPU_PROVIDES_ISR_IS_IN_PROGRESS == TRUE)
193bool _ISR_Is_in_progress( void );
194#else
195#define _ISR_Is_in_progress() \
196        (_ISR_Nest_level != 0)
197#endif
198
199#include <rtems/score/isr.inl>
200
201#ifdef __cplusplus
202}
203#endif
204
205/**@}*/
206
207#endif
208/* end of include file */
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