source: rtems/cpukit/score/include/rtems/score/isr.h @ d6154c7

4.104.114.84.95
Last change on this file since d6154c7 was d6154c7, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 29, 2004 at 4:41:13 PM

2004-03-29 Ralf Corsepius <ralf_corsepius@…>

  • score/include/rtems/debug.h, score/include/rtems/score/bitfield.h, score/include/rtems/score/chain.h, score/include/rtems/score/coremsg.h, score/include/rtems/score/coremutex.h, score/include/rtems/score/coresem.h, score/include/rtems/score/heap.h, score/include/rtems/score/interr.h, score/include/rtems/score/isr.h, score/include/rtems/score/mpci.h, score/include/rtems/score/mppkt.h, score/include/rtems/score/object.h, score/include/rtems/score/objectmp.h, score/include/rtems/score/priority.h, score/include/rtems/score/stack.h, score/include/rtems/score/states.h, score/include/rtems/score/thread.h, score/include/rtems/score/threadmp.h, score/include/rtems/score/threadq.h, score/include/rtems/score/tod.h, score/include/rtems/score/tqdata.h, score/include/rtems/score/userext.h, score/include/rtems/score/watchdog.h, score/include/rtems/score/wkspace.h, score/inline/rtems/score/address.inl, score/inline/rtems/score/coremsg.inl, score/inline/rtems/score/coresem.inl, score/inline/rtems/score/heap.inl, score/inline/rtems/score/isr.inl, score/inline/rtems/score/object.inl, score/inline/rtems/score/priority.inl, score/inline/rtems/score/stack.inl, score/inline/rtems/score/thread.inl, score/inline/rtems/score/tqdata.inl, score/inline/rtems/score/userext.inl, score/inline/rtems/score/wkspace.inl, score/macros/rtems/score/address.inl, score/macros/rtems/score/heap.inl, score/macros/rtems/score/object.inl, score/macros/rtems/score/priority.inl, score/macros/rtems/score/userext.inl: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 6.3 KB
Line 
1/*  isr.h
2 *
3 *  This include file contains all the constants and structures associated
4 *  with the management of processor interrupt levels.  This handler
5 *  supports interrupt critical sections, vectoring of user interrupt
6 *  handlers, nesting of interrupts, and manipulating interrupt levels.
7 *
8 *  COPYRIGHT (c) 1989-1999.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  $Id$
16 */
17
18#ifndef __ISR_h
19#define __ISR_h
20
21#ifdef __cplusplus
22extern "C" {
23#endif
24
25/*
26 *  The following type defines the control block used to manage
27 *  the interrupt level portion of the status register.
28 */
29
30typedef uint32_t   ISR_Level;
31
32/*
33 *  The following type defines the type used to manage the vectors.
34 */
35
36typedef uint32_t   ISR_Vector_number;
37
38/*
39 *  Return type for ISR Handler
40 */
41
42typedef void ISR_Handler;
43
44/*
45 *  Pointer to an ISR Handler
46 */
47
48#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
49typedef ISR_Handler ( *ISR_Handler_entry )(
50                 ISR_Vector_number,
51                 CPU_Interrupt_frame *
52             );
53#else
54typedef ISR_Handler ( *ISR_Handler_entry )(
55                 ISR_Vector_number
56             );
57#endif
58/*
59 *  This constant promotes out the number of vectors truly supported by
60 *  the current CPU being used.  This is usually the number of distinct vectors
61 *  the cpu can vector.
62 */
63 
64#define ISR_NUMBER_OF_VECTORS                CPU_INTERRUPT_NUMBER_OF_VECTORS
65
66/*
67 *  This constant promotes out the highest valid interrupt vector number.
68 */
69
70#define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER  CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER
71
72/*
73 *  The following is TRUE if signals have been sent to the currently
74 *  executing thread by an ISR handler.
75 */
76
77SCORE_EXTERN boolean    _ISR_Signals_to_thread_executing;
78
79/*
80 *  The following contains the interrupt service routine nest level.
81 *  When this variable is zero, a thread is executing.
82 */
83
84SCORE_EXTERN volatile uint32_t   _ISR_Nest_level;
85
86/*
87 *  The following declares the Vector Table.  Application
88 *  interrupt service routines are vectored by the ISR Handler via this table.
89 */
90
91SCORE_EXTERN ISR_Handler_entry *_ISR_Vector_table;
92
93/*
94 *  _ISR_Handler_initialization
95 *
96 *  DESCRIPTION:
97 *
98 *  This routine performs the initialization necessary for this handler.
99 */
100
101void _ISR_Handler_initialization ( void );
102
103/*
104 *  _ISR_Disable
105 *
106 *  DESCRIPTION:
107 *
108 *  This routine disables all interrupts so that a critical section
109 *  of code can be executing without being interrupted.  Upon return,
110 *  the argument _level will contain the previous interrupt mask level.
111 */
112
113#define _ISR_Disable( _level ) \
114        _CPU_ISR_Disable( _level )
115
116/*
117 *  _ISR_Enable
118 *
119 *  DESCRIPTION:
120 *
121 *  This routine enables interrupts to the previous interrupt mask
122 *  LEVEL.  It is used at the end of a critical section of code to
123 *  enable interrupts so they can be processed again.
124 */
125
126#define _ISR_Enable( _level ) \
127        _CPU_ISR_Enable( _level )
128
129/*
130 *  _ISR_Flash
131 *
132 *  DESCRIPTION:
133 *
134 *  This routine temporarily enables interrupts to the previous
135 *  interrupt mask level and then disables all interrupts so that
136 *  the caller can continue into the second part of a critical
137 *  section.  This routine is used to temporarily enable interrupts
138 *  during a long critical section.  It is used in long sections of
139 *  critical code when a point is reached at which interrupts can
140 *  be temporarily enabled.  Deciding where to flash interrupts
141 *  in a long critical section is often difficult and the point
142 *  must be selected with care to insure that the critical section
143 *  properly protects itself.
144 */
145
146#define _ISR_Flash( _level ) \
147        _CPU_ISR_Flash( _level )
148
149/*
150 *  _ISR_Install_vector
151 *
152 *  DESCRIPTION:
153 *
154 *  This routine installs new_handler as the interrupt service routine
155 *  for the specified vector.  The previous interrupt service routine is
156 *  returned as old_handler.
157 */
158
159#define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \
160  _CPU_ISR_install_vector( _vector, _new_handler, _old_handler )
161
162/*
163 *  _ISR_Get_level
164 *
165 *  DESCRIPTION:
166 *
167 *  This routine returns the current interrupt level.
168 */
169 
170#define _ISR_Get_level() \
171        _CPU_ISR_Get_level()
172 
173/*
174 *  _ISR_Set_level
175 *
176 *  DESCRIPTION:
177 *
178 *  This routine sets the current interrupt level to that specified
179 *  by new_level.  The new interrupt level is effective when the
180 *  routine exits.
181 */
182
183#define _ISR_Set_level( _new_level ) \
184        _CPU_ISR_Set_level( _new_level )
185
186/*
187 *  _ISR_Handler
188 *
189 *  DESCRIPTION:
190 *
191 *  This routine is the interrupt dispatcher.  ALL interrupts
192 *  are vectored to this routine so that minimal context can be saved
193 *  and setup performed before the application's high-level language
194 *  interrupt service routine is invoked.   After the application's
195 *  interrupt service routine returns control to this routine, it
196 *  will determine if a thread dispatch is necessary.  If so, it will
197 *  insure that the necessary thread scheduling operations are
198 *  performed when the outermost interrupt service routine exits.
199 *
200 *  NOTE:  Implemented in assembly language.
201 */
202
203void _ISR_Handler( void );
204
205/*
206 *  _ISR_Dispatch
207 *
208 *  DESCRIPTION:
209 *
210 *  This routine provides a wrapper so that the routine
211 *  _Thread_Dispatch can be invoked when a reschedule is necessary
212 *  at the end of the outermost interrupt service routine.  This
213 *  wrapper is necessary to establish the processor context needed
214 *  by _Thread_Dispatch and to save the processor context which is
215 *  corrupted by _Thread_Dispatch.  This context typically consists
216 *  of registers which are not preserved across routine invocations.
217 *
218 *  NOTE:  Implemented in assembly language.
219 */
220
221void _ISR_Dispatch( void );
222
223/*PAGE
224 *
225 *  _ISR_Is_in_progress
226 *
227 *  DESCRIPTION:
228 *
229 *  This function returns TRUE if the processor is currently servicing
230 *  and interrupt and FALSE otherwise.   A return value of TRUE indicates
231 *  that the caller is an interrupt service routine, NOT a thread.  The
232 */
233
234#if (CPU_PROVIDES_ISR_IS_IN_PROGRESS == TRUE)
235boolean _ISR_Is_in_progress( void );
236#else
237#define _ISR_Is_in_progress() \
238        (_ISR_Nest_level != 0)
239#endif
240
241#include <rtems/score/isr.inl>
242
243#ifdef __cplusplus
244}
245#endif
246
247#endif
248/* end of include file */
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