1 | /** |
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2 | * @file rtems/score/isr.h |
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3 | * |
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4 | * This include file contains all the constants and structures associated |
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5 | * with the management of processor interrupt levels. This handler |
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6 | * supports interrupt critical sections, vectoring of user interrupt |
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7 | * handlers, nesting of interrupts, and manipulating interrupt levels. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * COPYRIGHT (c) 1989-2012. |
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12 | * On-Line Applications Research Corporation (OAR). |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.com/license/LICENSE. |
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17 | */ |
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18 | |
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19 | #ifndef _RTEMS_SCORE_ISR_H |
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20 | #define _RTEMS_SCORE_ISR_H |
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21 | |
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22 | #include <rtems/score/percpu.h> |
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23 | |
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24 | /** |
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25 | * @defgroup ScoreISR ISR Handler |
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26 | * |
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27 | * @ingroup Score |
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28 | * |
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29 | * This handler encapsulates functionality which provides the foundation |
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30 | * ISR services used in all of the APIs supported by RTEMS. |
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31 | * |
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32 | * The ISR Nest level counter variable is maintained as part of the |
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33 | * per cpu data structure. |
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34 | */ |
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35 | /**@{*/ |
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36 | |
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37 | #ifdef __cplusplus |
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38 | extern "C" { |
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39 | #endif |
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40 | |
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41 | /** |
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42 | * The following type defines the type used to manage the vectors. |
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43 | */ |
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44 | typedef uint32_t ISR_Vector_number; |
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45 | |
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46 | /** |
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47 | * Return type for ISR Handler |
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48 | */ |
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49 | typedef void ISR_Handler; |
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50 | |
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51 | #if (CPU_SIMPLE_VECTORED_INTERRUPTS == FALSE) |
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52 | |
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53 | typedef void * ISR_Handler_entry; |
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54 | |
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55 | #else |
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56 | /** |
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57 | * Pointer to an ISR Handler |
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58 | */ |
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59 | #if (CPU_ISR_PASSES_FRAME_POINTER == 1) |
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60 | typedef ISR_Handler ( *ISR_Handler_entry )( |
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61 | ISR_Vector_number, |
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62 | CPU_Interrupt_frame * |
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63 | ); |
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64 | #else |
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65 | typedef ISR_Handler ( *ISR_Handler_entry )( |
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66 | ISR_Vector_number |
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67 | ); |
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68 | #endif |
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69 | |
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70 | /** |
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71 | * This constant promotes out the number of vectors truly supported by |
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72 | * the current CPU being used. This is usually the number of distinct vectors |
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73 | * the cpu can vector. |
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74 | */ |
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75 | #define ISR_NUMBER_OF_VECTORS CPU_INTERRUPT_NUMBER_OF_VECTORS |
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76 | |
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77 | /** |
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78 | * This constant promotes out the highest valid interrupt vector number. |
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79 | */ |
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80 | #define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER |
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81 | |
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82 | /** |
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83 | * The following declares the Vector Table. Application |
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84 | * interrupt service routines are vectored by the ISR Handler via this table. |
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85 | */ |
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86 | SCORE_EXTERN ISR_Handler_entry *_ISR_Vector_table; |
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87 | #endif |
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88 | |
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89 | /** |
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90 | * @brief Initialize the ISR handler |
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91 | * |
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92 | * This routine performs the initialization necessary for the ISR handler. |
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93 | */ |
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94 | void _ISR_Handler_initialization ( void ); |
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95 | |
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96 | /** |
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97 | * @brief Disable Interrupts on This Core |
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98 | * |
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99 | * This routine disables all interrupts so that a critical section |
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100 | * of code can be executing without being interrupted. |
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101 | * |
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102 | * @return The argument @a _level will contain the previous interrupt |
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103 | * mask level. |
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104 | */ |
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105 | #define _ISR_Disable_on_this_core( _level ) \ |
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106 | do { \ |
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107 | _CPU_ISR_Disable( _level ); \ |
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108 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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109 | } while (0) |
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110 | |
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111 | /** |
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112 | * @brief Enable Interrupts on This Core |
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113 | * |
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114 | * This routine enables interrupts to the previous interrupt mask |
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115 | * LEVEL. It is used at the end of a critical section of code to |
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116 | * enable interrupts so they can be processed again. |
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117 | * |
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118 | * @param[in] level contains the interrupt level mask level |
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119 | * previously returned by @ref _ISR_Disable_on_this_core. |
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120 | */ |
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121 | #define _ISR_Enable_on_this_core( _level ) \ |
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122 | do { \ |
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123 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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124 | _CPU_ISR_Enable( _level ); \ |
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125 | } while (0) |
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126 | |
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127 | /** |
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128 | * @brief Temporarily Enable Interrupts on This Core |
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129 | * |
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130 | * This routine temporarily enables interrupts to the previous |
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131 | * interrupt mask level and then disables all interrupts so that |
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132 | * the caller can continue into the second part of a critical |
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133 | * section. |
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134 | * |
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135 | * This routine is used to temporarily enable interrupts |
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136 | * during a long critical section. It is used in long sections of |
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137 | * critical code when a point is reached at which interrupts can |
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138 | * be temporarily enabled. Deciding where to flash interrupts |
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139 | * in a long critical section is often difficult and the point |
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140 | * must be selected with care to ensure that the critical section |
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141 | * properly protects itself. |
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142 | * |
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143 | * @param[in] level contains the interrupt level mask level |
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144 | * previously returned by @ref _ISR_Disable_on_this_core. |
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145 | */ |
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146 | #define _ISR_Flash_on_this_core( _level ) \ |
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147 | do { \ |
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148 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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149 | _CPU_ISR_Flash( _level ); \ |
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150 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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151 | } while (0) |
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152 | |
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153 | #if defined(RTEMS_SMP) |
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154 | |
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155 | /** |
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156 | * @brief Initialize SMP Interrupt Critical Section Support |
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157 | * |
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158 | * This method initializes the variables required by the SMP implementation |
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159 | * of interrupt critical section management. |
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160 | */ |
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161 | void _ISR_SMP_Initialize(void); |
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162 | |
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163 | /** |
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164 | * @brief Enter Interrupt Critical Section on SMP System |
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165 | * |
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166 | * This method is used to enter an interrupt critical section that |
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167 | * is honored across all cores in an SMP system. |
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168 | * |
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169 | * @return This method returns the previous interrupt mask level. |
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170 | */ |
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171 | ISR_Level _ISR_SMP_Disable(void); |
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172 | |
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173 | /** |
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174 | * @brief Exit Interrupt Critical Section on SMP System |
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175 | * |
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176 | * This method is used to exit an interrupt critical section that |
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177 | * is honored across all cores in an SMP system. |
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178 | * |
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179 | * @param[in] level contains the interrupt level mask level |
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180 | * previously returned by @ref _ISR_SMP_Disable. |
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181 | */ |
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182 | void _ISR_SMP_Enable(ISR_Level level); |
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183 | |
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184 | /** |
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185 | * @brief Temporarily Exit Interrupt Critical Section on SMP System |
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186 | * |
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187 | * This method is used to temporarily exit an interrupt critical section |
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188 | * that is honored across all cores in an SMP system. |
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189 | * |
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190 | * @param[in] level contains the interrupt level mask level |
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191 | * previously returned by @ref _ISR_SMP_Disable. |
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192 | */ |
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193 | void _ISR_SMP_Flash(ISR_Level level); |
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194 | |
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195 | /** |
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196 | * @brief Enter SMP interrupt code |
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197 | * |
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198 | * This method is used to enter the SMP interrupt section. |
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199 | * |
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200 | * @return This method returns the isr level. |
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201 | */ |
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202 | int _ISR_SMP_Enter(void); |
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203 | |
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204 | /** |
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205 | * @brief Exit SMP interrupt code |
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206 | * |
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207 | * This method is used to exit the SMP interrupt. |
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208 | * |
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209 | * @return This method returns 0 on a simple return and returns 1 on a |
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210 | * dispatching return. |
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211 | */ |
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212 | int _ISR_SMP_Exit(void); |
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213 | |
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214 | #endif |
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215 | |
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216 | /** |
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217 | * @brief Enter Interrupt Disable Critical Section |
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218 | * |
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219 | * This routine enters an interrupt disable critical section. When |
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220 | * in an SMP configuration, this involves obtaining a spinlock to ensure |
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221 | * that only one core is inside an interrupt disable critical section. |
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222 | * When on a single core system, this only involves disabling local |
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223 | * CPU interrupts. |
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224 | * |
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225 | * @return The argument @a _level will contain the previous interrupt |
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226 | * mask level. |
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227 | */ |
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228 | #if defined(RTEMS_SMP) |
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229 | #define _ISR_Disable( _level ) \ |
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230 | _level = _ISR_SMP_Disable(); |
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231 | #else |
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232 | #define _ISR_Disable( _level ) \ |
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233 | _ISR_Disable_on_this_core( _level ); |
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234 | #endif |
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235 | |
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236 | /** |
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237 | * @brief Exits Interrupt Disable Critical Section |
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238 | * |
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239 | * This routine exits an interrupt disable critical section. When |
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240 | * in an SMP configuration, this involves releasing a spinlock. |
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241 | * When on a single core system, this only involves disabling local |
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242 | * CPU interrupts. |
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243 | * |
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244 | * @return The argument @a _level will contain the previous interrupt |
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245 | * mask level. |
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246 | */ |
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247 | #if defined(RTEMS_SMP) |
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248 | #define _ISR_Enable( _level ) \ |
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249 | _ISR_SMP_Enable( _level ); |
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250 | #else |
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251 | #define _ISR_Enable( _level ) \ |
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252 | _ISR_Enable_on_this_core( _level ); |
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253 | #endif |
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254 | |
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255 | /** |
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256 | * @brief Temporarily Exit Interrupt Disable Critical Section |
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257 | * |
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258 | * This routine is used to temporarily enable interrupts |
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259 | * during a long critical section. It is used in long sections of |
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260 | * critical code when a point is reached at which interrupts can |
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261 | * be temporarily enabled. Deciding where to flash interrupts |
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262 | * in a long critical section is often difficult and the point |
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263 | * must be selected with care to ensure that the critical section |
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264 | * properly protects itself. |
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265 | * |
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266 | * @return The argument @a _level will contain the previous interrupt |
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267 | * mask level. |
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268 | */ |
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269 | #if defined(RTEMS_SMP) |
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270 | #define _ISR_Flash( _level ) \ |
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271 | _ISR_SMP_Flash( _level ); |
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272 | #else |
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273 | #define _ISR_Flash( _level ) \ |
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274 | _ISR_Flash_on_this_core( _level ); |
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275 | #endif |
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276 | |
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277 | /** |
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278 | * @brief Install Interrupt Handler Vector |
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279 | * |
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280 | * This routine installs new_handler as the interrupt service routine |
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281 | * for the specified vector. The previous interrupt service routine is |
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282 | * returned as old_handler. |
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283 | * |
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284 | * @param[in] _vector is the vector number |
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285 | * @param[in] _new_handler is ISR handler to install |
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286 | * @param[in] _old_handler is a pointer to a variable which will be set |
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287 | * to the old handler |
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288 | * |
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289 | * @return *_old_handler will be set to the old ISR handler |
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290 | */ |
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291 | #define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \ |
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292 | _CPU_ISR_install_vector( _vector, _new_handler, _old_handler ) |
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293 | |
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294 | /** |
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295 | * @brief Return Current Interrupt Level |
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296 | * |
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297 | * This routine returns the current interrupt level. |
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298 | * |
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299 | * @return This method returns the current level. |
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300 | */ |
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301 | #define _ISR_Get_level() \ |
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302 | _CPU_ISR_Get_level() |
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303 | |
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304 | /** |
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305 | * @brief Set Current Interrupt Level |
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306 | * |
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307 | * This routine sets the current interrupt level to that specified |
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308 | * by @a _new_level. The new interrupt level is effective when the |
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309 | * routine exits. |
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310 | * |
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311 | * @param[in] _new_level contains the desired interrupt level. |
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312 | */ |
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313 | #define _ISR_Set_level( _new_level ) \ |
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314 | do { \ |
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315 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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316 | _CPU_ISR_Set_level( _new_level ); \ |
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317 | RTEMS_COMPILER_MEMORY_BARRIER(); \ |
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318 | } while (0) |
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319 | |
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320 | /** |
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321 | * @brief ISR Handler or Dispatcher |
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322 | * |
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323 | * This routine is the interrupt dispatcher. ALL interrupts |
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324 | * are vectored to this routine so that minimal context can be saved |
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325 | * and setup performed before the application's high-level language |
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326 | * interrupt service routine is invoked. After the application's |
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327 | * interrupt service routine returns control to this routine, it |
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328 | * will determine if a thread dispatch is necessary. If so, it will |
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329 | * ensure that the necessary thread scheduling operations are |
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330 | * performed when the outermost interrupt service routine exits. |
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331 | * |
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332 | * @note Typically implemented in assembly language. |
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333 | */ |
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334 | void _ISR_Handler( void ); |
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335 | |
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336 | /** |
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337 | * @brief ISR Wrapper for Thread Dispatcher |
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338 | * |
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339 | * This routine provides a wrapper so that the routine |
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340 | * @ref _Thread_Dispatch can be invoked when a reschedule is necessary |
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341 | * at the end of the outermost interrupt service routine. This |
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342 | * wrapper is necessary to establish the processor context needed |
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343 | * by _Thread_Dispatch and to save the processor context which is |
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344 | * corrupted by _Thread_Dispatch. This context typically consists |
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345 | * of registers which are not preserved across routine invocations. |
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346 | * |
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347 | * @note Typically mplemented in assembly language. |
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348 | */ |
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349 | void _ISR_Dispatch( void ); |
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350 | |
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351 | /** |
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352 | * @brief Is an ISR in Progress |
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353 | * |
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354 | * This function returns true if the processor is currently servicing |
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355 | * and interrupt and false otherwise. A return value of true indicates |
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356 | * that the caller is an interrupt service routine, NOT a thread. |
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357 | * |
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358 | * @return This methods returns true when called from an ISR. |
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359 | */ |
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360 | #if (CPU_PROVIDES_ISR_IS_IN_PROGRESS == TRUE) |
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361 | bool _ISR_Is_in_progress( void ); |
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362 | #else |
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363 | #define _ISR_Is_in_progress() \ |
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364 | (_ISR_Nest_level != 0) |
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365 | #endif |
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366 | |
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367 | #include <rtems/score/isr.inl> |
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368 | |
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369 | #ifdef __cplusplus |
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370 | } |
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371 | #endif |
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372 | |
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373 | /**@}*/ |
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374 | |
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375 | #endif |
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376 | /* end of include file */ |
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