source: rtems/cpukit/score/include/rtems/score/isr.h @ 5e9b32b

4.104.114.84.95
Last change on this file since 5e9b32b was 5e9b32b, checked in by Joel Sherrill <joel.sherrill@…>, on 09/26/95 at 19:27:15

posix support initially added

  • Property mode set to 100644
File size: 6.4 KB
Line 
1/*  isr.h
2 *
3 *  This include file contains all the constants and structures associated
4 *  with the management of processor interrupt levels.  This handler
5 *  supports interrupt critical sections, vectoring of user interrupt
6 *  handlers, nesting of interrupts, and manipulating interrupt levels.
7 *
8 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
9 *  On-Line Applications Research Corporation (OAR).
10 *  All rights assigned to U.S. Government, 1994.
11 *
12 *  This material may be reproduced by or for the U.S. Government pursuant
13 *  to the copyright license under the clause at DFARS 252.227-7013.  This
14 *  notice must appear in all copies of this file and its derivatives.
15 *
16 *  $Id$
17 */
18
19#ifndef __ISR_h
20#define __ISR_h
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/*
27 *  The following type defines the control block used to manage
28 *  the interrupt level portion of the status register.
29 */
30
31typedef unsigned32 ISR_Level;
32
33/*
34 *  The following type defines the type used to manage the vectors.
35 */
36
37typedef unsigned32 ISR_Vector_number;
38
39/*
40 *  Return type for ISR Handler
41 */
42
43typedef void ISR_Handler;
44
45/*
46 *  Pointer to an ISR Handler
47 */
48
49typedef ISR_Handler ( *ISR_Handler_entry )(
50                 ISR_Vector_number
51             );
52/*
53 *  This constant promotes out the number of vectors supported by
54 *  the current CPU being used.
55 */
56 
57#define ISR_NUMBER_OF_VECTORS    CPU_INTERRUPT_NUMBER_OF_VECTORS
58
59/*
60 *  The following is TRUE if signals have been sent to the currently
61 *  executing thread by an ISR handler.
62 */
63
64EXTERN boolean    _ISR_Signals_to_thread_executing;
65
66/*
67 *  The following contains the interrupt service routine nest level.
68 *  When this variable is zero, a thread is executing.
69 */
70
71EXTERN unsigned32 _ISR_Nest_level;
72
73/*
74 *  The following declares the Vector Table.  Application
75 *  interrupt service routines are vectored by the ISR Handler via this table.
76 */
77
78EXTERN ISR_Handler_entry _ISR_Vector_table[CPU_INTERRUPT_NUMBER_OF_VECTORS];
79
80/*
81 *  _ISR_Handler_initialization
82 *
83 *  DESCRIPTION:
84 *
85 *  This routine performs the initialization necessary for this handler.
86 */
87
88void _ISR_Handler_initialization ( void );
89
90/*
91 *  _ISR_Disable
92 *
93 *  DESCRIPTION:
94 *
95 *  This routine disables all interrupts so that a critical section
96 *  of code can be executing without being interrupted.  Upon return,
97 *  the argument _level will contain the previous interrupt mask level.
98 */
99
100#define _ISR_Disable( _level ) \
101        _CPU_ISR_Disable( _level )
102
103/*
104 *  _ISR_Enable
105 *
106 *  DESCRIPTION:
107 *
108 *  This routine enables interrupts to the previous interrupt mask
109 *  LEVEL.  It is used at the end of a critical section of code to
110 *  enable interrupts so they can be processed again.
111 */
112
113#define _ISR_Enable( _level ) \
114        _CPU_ISR_Enable( _level )
115
116/*
117 *  _ISR_Flash
118 *
119 *  DESCRIPTION:
120 *
121 *  This routine temporarily enables interrupts to the previous
122 *  interrupt mask level and then disables all interrupts so that
123 *  the caller can continue into the second part of a critical
124 *  section.  This routine is used to temporarily enable interrupts
125 *  during a long critical section.  It is used in long sections of
126 *  critical code when a point is reached at which interrupts can
127 *  be temporarily enabled.  Deciding where to flash interrupts
128 *  in a long critical section is often difficult and the point
129 *  must be selected with care to insure that the critical section
130 *  properly protects itself.
131 */
132
133#define _ISR_Flash( _level ) \
134        _CPU_ISR_Flash( _level )
135
136/*
137 *  _ISR_Is_in_progress
138 *
139 *  DESCRIPTION:
140 *
141 *  This function returns TRUE if the processor is currently servicing
142 *  and interrupt and FALSE otherwise.   A return value of TRUE indicates
143 *  that the caller is an interrupt service routine, NOT a thread.  The
144 *  directives available to an interrupt service routine are restricted.
145 */
146
147STATIC INLINE boolean _ISR_Is_in_progress( void );
148
149/*
150 *  _ISR_Install_vector
151 *
152 *  DESCRIPTION:
153 *
154 *  This routine installs new_handler as the interrupt service routine
155 *  for the specified vector.  The previous interrupt service routine is
156 *  returned as old_handler.
157 */
158
159#define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \
160  _CPU_ISR_install_vector( _vector, _new_handler, _old_handler )
161
162/*
163 *  _ISR_Get_level
164 *
165 *  DESCRIPTION:
166 *
167 *  This routine returns the current interrupt level.
168 */
169 
170#define _ISR_Get_level() \
171        _CPU_ISR_Get_level()
172 
173/*
174 *  _ISR_Set_level
175 *
176 *  DESCRIPTION:
177 *
178 *  This routine sets the current interrupt level to that specified
179 *  by new_level.  The new interrupt level is effective when the
180 *  routine exits.
181 */
182
183#define _ISR_Set_level( _new_level ) \
184        _CPU_ISR_Set_level( _new_level )
185
186/*
187 *  _ISR_Is_vector_number_valid
188 *
189 *  DESCRIPTION:
190 *
191 *  This function returns TRUE if the vector is a valid vector number
192 *  for this processor and FALSE otherwise.
193 */
194
195STATIC INLINE boolean _ISR_Is_vector_number_valid (
196  ISR_Vector_number   vector
197);
198
199/*
200 *  _ISR_Is_valid_user_handler
201 *
202 *  DESCRIPTION:
203 *
204 *  This function returns TRUE if handler is the entry point of a valid
205 *  use interrupt service routine and FALSE otherwise.
206 */
207
208STATIC INLINE boolean _ISR_Is_valid_user_handler (
209  void *handler
210);
211
212/*
213 *  _ISR_Handler
214 *
215 *  DESCRIPTION:
216 *
217 *  This routine is the interrupt dispatcher.  ALL interrupts
218 *  are vectored to this routine so that minimal context can be saved
219 *  and setup performed before the application's high-level language
220 *  interrupt service routine is invoked.   After the application's
221 *  interrupt service routine returns control to this routine, it
222 *  will determine if a thread dispatch is necessary.  If so, it will
223 *  insure that the necessary thread scheduling operations are
224 *  performed when the outermost interrupt service routine exits.
225 *
226 *  NOTE:  Implemented in assembly language.
227 */
228
229void _ISR_Handler( void );
230
231/*
232 *  _ISR_Dispatch
233 *
234 *  DESCRIPTION:
235 *
236 *  This routine provides a wrapper so that the routine
237 *  _Thread_Dispatch can be invoked when a reschedule is necessary
238 *  at the end of the outermost interrupt service routine.  This
239 *  wrapper is necessary to establish the processor context needed
240 *  by _Thread_Dispatch and to save the processor context which is
241 *  corrupted by _Thread_Dispatch.  This context typically consists
242 *  of registers which are not preserved across routine invocations.
243 *
244 *  NOTE:  Implemented in assembly language.
245 */
246
247void _ISR_Dispatch( void );
248
249#include <rtems/score/isr.inl>
250
251#ifdef __cplusplus
252}
253#endif
254
255#endif
256/* end of include file */
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