source: rtems/cpukit/score/include/rtems/score/isr.h @ 32eba74

4.115
Last change on this file since 32eba74 was 32eba74, checked in by Jennifer Averett <Jennifer.Averett@…>, on Aug 1, 2011 at 7:21:47 PM

2011-08-01 Jennifer Averett <Jennifer.Averett@…>

  • score/include/rtems/score/isr.h: Cleaned up comments.
  • Property mode set to 100644
File size: 7.2 KB
Line 
1/**
2 *  @file  rtems/score/isr.h
3 *
4 *  This include file contains all the constants and structures associated
5 *  with the management of processor interrupt levels.  This handler
6 *  supports interrupt critical sections, vectoring of user interrupt
7 *  handlers, nesting of interrupts, and manipulating interrupt levels.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2006.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *  $Id$
19 */
20
21#ifndef _RTEMS_SCORE_ISR_H
22#define _RTEMS_SCORE_ISR_H
23
24#include <rtems/score/percpu.h>
25
26/**
27 *  @defgroup ScoreISR ISR Handler
28 *
29 *  @ingroup Score
30 *
31 *  This handler encapsulates functionality which provides the foundation
32 *  ISR services used in all of the APIs supported by RTEMS.
33 *
34 *  The ISR Nest level counter variable is maintained as part of the
35 *  per cpu data structure.
36 */
37/**@{*/
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43/**
44 *  The following type defines the type used to manage the vectors.
45 */
46typedef uint32_t   ISR_Vector_number;
47
48/**
49 *  Return type for ISR Handler
50 */
51typedef void ISR_Handler;
52
53/**
54 *  Pointer to an ISR Handler
55 */
56#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
57typedef ISR_Handler ( *ISR_Handler_entry )(
58                 ISR_Vector_number,
59                 CPU_Interrupt_frame *
60             );
61#else
62typedef ISR_Handler ( *ISR_Handler_entry )(
63                 ISR_Vector_number
64             );
65#endif
66
67/**
68 *  This constant promotes out the number of vectors truly supported by
69 *  the current CPU being used.  This is usually the number of distinct vectors
70 *  the cpu can vector.
71 */
72#define ISR_NUMBER_OF_VECTORS                CPU_INTERRUPT_NUMBER_OF_VECTORS
73
74/**
75 *  This constant promotes out the highest valid interrupt vector number.
76 */
77#define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER  CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER
78
79#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
80/**
81 *  The following declares the Vector Table.  Application
82 *  interrupt service routines are vectored by the ISR Handler via this table.
83 */
84SCORE_EXTERN ISR_Handler_entry *_ISR_Vector_table;
85#endif
86
87/**
88 *  This routine performs the initialization necessary for this handler.
89 */
90void _ISR_Handler_initialization ( void );
91
92/**
93 *  @brief Disable Interrupts
94 *
95 *  This routine disables all interrupts so that a critical section
96 *  of code can be executing without being interrupted.
97 *
98 *  @return The argument @a _level will contain the previous interrupt
99 *          mask level.
100 */
101#define _ISR_Disable( _level ) \
102  do { \
103    _CPU_ISR_Disable( _level ); \
104    RTEMS_COMPILER_MEMORY_BARRIER(); \
105  } while (0)
106
107/**
108 *  @brief Enable Interrupts
109 *
110 *  This routine enables interrupts to the previous interrupt mask
111 *  LEVEL.  It is used at the end of a critical section of code to
112 *  enable interrupts so they can be processed again.
113 *
114 *  @param[in] level contains the interrupt level mask level
115 *             previously returned by @ref _ISR_Disable_on_core.
116 */
117#define _ISR_Enable( _level ) \
118  do { \
119    RTEMS_COMPILER_MEMORY_BARRIER(); \
120    _CPU_ISR_Enable( _level ); \
121  } while (0)
122
123/**
124 *  @brief Temporarily Enable Interrupts
125 *
126 *  This routine temporarily enables interrupts to the previous
127 *  interrupt mask level and then disables all interrupts so that
128 *  the caller can continue into the second part of a critical
129 *  section.
130 *
131 *  This routine is used to temporarily enable interrupts
132 *  during a long critical section.  It is used in long sections of
133 *  critical code when a point is reached at which interrupts can
134 *  be temporarily enabled.  Deciding where to flash interrupts
135 *  in a long critical section is often difficult and the point
136 *  must be selected with care to ensure that the critical section
137 *  properly protects itself.
138 *
139 *  @param[in] level contains the interrupt level mask level
140 *             previously returned by @ref _ISR_Disable_on_core.
141 */
142#define _ISR_Flash( _level ) \
143  do { \
144    RTEMS_COMPILER_MEMORY_BARRIER(); \
145    _CPU_ISR_Flash( _level ); \
146    RTEMS_COMPILER_MEMORY_BARRIER(); \
147  } while (0)
148
149/**
150 *  @brief Install Interrupt Handler Vector
151 *
152 *  This routine installs new_handler as the interrupt service routine
153 *  for the specified vector.  The previous interrupt service routine is
154 *  returned as old_handler.
155 *
156 *  @param[in] _vector is the vector number
157 *  @param[in] _new_handler is ISR handler to install
158 *  @param[in] _old_handler is a pointer to a variable which will be set
159 *             to the old handler
160 *
161 *  @return *_old_handler will be set to the old ISR handler
162 */
163#define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \
164  _CPU_ISR_install_vector( _vector, _new_handler, _old_handler )
165
166/**
167 *  @brief Return Current Interrupt Level
168 *
169 *  This routine returns the current interrupt level.
170 *
171 *  @return This method returns the current level.
172 */
173#define _ISR_Get_level() \
174        _CPU_ISR_Get_level()
175
176/**
177 *  @brief Set Current Interrupt Level
178 *
179 *  This routine sets the current interrupt level to that specified
180 *  by @a _new_level.  The new interrupt level is effective when the
181 *  routine exits.
182 *
183 *  @param[in] _new_level contains the desired interrupt level.
184 */
185#define _ISR_Set_level( _new_level ) \
186  do { \
187    RTEMS_COMPILER_MEMORY_BARRIER();  \
188    _CPU_ISR_Set_level( _new_level ); \
189    RTEMS_COMPILER_MEMORY_BARRIER();  \
190  } while (0)
191
192/**
193 *  @brief ISR Handler or Dispatcher
194 *
195 *  This routine is the interrupt dispatcher.  ALL interrupts
196 *  are vectored to this routine so that minimal context can be saved
197 *  and setup performed before the application's high-level language
198 *  interrupt service routine is invoked.   After the application's
199 *  interrupt service routine returns control to this routine, it
200 *  will determine if a thread dispatch is necessary.  If so, it will
201 *  ensure that the necessary thread scheduling operations are
202 *  performed when the outermost interrupt service routine exits.
203 *
204 *  @note  Implemented in assembly language.
205 */
206void _ISR_Handler( void );
207
208/**
209 *  @brief ISR Wrapper for Thread Dispatcher
210 *
211 *  This routine provides a wrapper so that the routine
212 *  @ref _Thread_Dispatch can be invoked when a reschedule is necessary
213 *  at the end of the outermost interrupt service routine.  This
214 *  wrapper is necessary to establish the processor context needed
215 *  by _Thread_Dispatch and to save the processor context which is
216 *  corrupted by _Thread_Dispatch.  This context typically consists
217 *  of registers which are not preserved across routine invocations.
218 *
219 *  @note  Typically mplemented in assembly language.
220 */
221void _ISR_Dispatch( void );
222
223/**
224 *  @brief Is an ISR in Progress
225 *
226 *  This function returns true if the processor is currently servicing
227 *  and interrupt and false otherwise.   A return value of true indicates
228 *  that the caller is an interrupt service routine, NOT a thread.
229 *
230 *  @return This methods returns true when called from an ISR.
231 */
232#if (CPU_PROVIDES_ISR_IS_IN_PROGRESS == TRUE)
233  bool _ISR_Is_in_progress( void );
234#else
235  #define _ISR_Is_in_progress() \
236          (_ISR_Nest_level != 0)
237#endif
238
239#include <rtems/score/isr.inl>
240
241#ifdef __cplusplus
242}
243#endif
244
245/**@}*/
246
247#endif
248/* end of include file */
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