source: rtems/cpukit/score/include/rtems/score/isr.h @ 11874561

4.104.114.84.95
Last change on this file since 11874561 was 11874561, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/21/04 at 07:17:38

Adjust doxygen @file.

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1/**
2 *  @file  rtems/score/isr.h
3 *
4 *  This include file contains all the constants and structures associated
5 *  with the management of processor interrupt levels.  This handler
6 *  supports interrupt critical sections, vectoring of user interrupt
7 *  handlers, nesting of interrupts, and manipulating interrupt levels.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2004.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *  $Id$
19 */
20
21#ifndef __ISR_h
22#define __ISR_h
23
24/**
25 *  @defgroup ScoreISR ISR Handler
26 *
27 *  This group contains functionality which provides the foundation
28 *  ISR services used in all of the APIs supported by RTEMS.
29 */
30/**@{*/
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36/**
37 *  The following type defines the control block used to manage
38 *  the interrupt level portion of the status register.
39 */
40typedef uint32_t   ISR_Level;
41
42/**
43 *  The following type defines the type used to manage the vectors.
44 */
45typedef uint32_t   ISR_Vector_number;
46
47/**
48 *  Return type for ISR Handler
49 */
50typedef void ISR_Handler;
51
52/**
53 *  Pointer to an ISR Handler
54 */
55#if (CPU_ISR_PASSES_FRAME_POINTER == 1)
56typedef ISR_Handler ( *ISR_Handler_entry )(
57                 ISR_Vector_number,
58                 CPU_Interrupt_frame *
59             );
60#else
61typedef ISR_Handler ( *ISR_Handler_entry )(
62                 ISR_Vector_number
63             );
64#endif
65
66/**
67 *  This constant promotes out the number of vectors truly supported by
68 *  the current CPU being used.  This is usually the number of distinct vectors
69 *  the cpu can vector.
70 */
71#define ISR_NUMBER_OF_VECTORS                CPU_INTERRUPT_NUMBER_OF_VECTORS
72
73/**
74 *  This constant promotes out the highest valid interrupt vector number.
75 */
76#define ISR_INTERRUPT_MAXIMUM_VECTOR_NUMBER  CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER
77
78/**
79 *  The following is TRUE if signals have been sent to the currently
80 *  executing thread by an ISR handler.
81 */
82SCORE_EXTERN boolean    _ISR_Signals_to_thread_executing;
83
84/**
85 *  The following contains the interrupt service routine nest level.
86 *  When this variable is zero, a thread is executing.
87 */
88SCORE_EXTERN volatile uint32_t   _ISR_Nest_level;
89
90/**
91 *  The following declares the Vector Table.  Application
92 *  interrupt service routines are vectored by the ISR Handler via this table.
93 */
94SCORE_EXTERN ISR_Handler_entry *_ISR_Vector_table;
95
96/**
97 *  This routine performs the initialization necessary for this handler.
98 */
99void _ISR_Handler_initialization ( void );
100
101/**
102 *  This routine disables all interrupts so that a critical section
103 *  of code can be executing without being interrupted.  Upon return,
104 *  the argument _level will contain the previous interrupt mask level.
105 */
106#define _ISR_Disable( _level ) \
107        _CPU_ISR_Disable( _level )
108
109/**
110 *  This routine enables interrupts to the previous interrupt mask
111 *  LEVEL.  It is used at the end of a critical section of code to
112 *  enable interrupts so they can be processed again.
113 */
114#define _ISR_Enable( _level ) \
115        _CPU_ISR_Enable( _level )
116
117/**
118 *  This routine temporarily enables interrupts to the previous
119 *  interrupt mask level and then disables all interrupts so that
120 *  the caller can continue into the second part of a critical
121 *  section.  This routine is used to temporarily enable interrupts
122 *  during a long critical section.  It is used in long sections of
123 *  critical code when a point is reached at which interrupts can
124 *  be temporarily enabled.  Deciding where to flash interrupts
125 *  in a long critical section is often difficult and the point
126 *  must be selected with care to insure that the critical section
127 *  properly protects itself.
128 */
129#define _ISR_Flash( _level ) \
130        _CPU_ISR_Flash( _level )
131
132/**
133 *  This routine installs new_handler as the interrupt service routine
134 *  for the specified vector.  The previous interrupt service routine is
135 *  returned as old_handler.
136 */
137#define _ISR_Install_vector( _vector, _new_handler, _old_handler ) \
138  _CPU_ISR_install_vector( _vector, _new_handler, _old_handler )
139
140/**
141 *  This routine returns the current interrupt level.
142 */
143#define _ISR_Get_level() \
144        _CPU_ISR_Get_level()
145
146/**
147 *  This routine sets the current interrupt level to that specified
148 *  by new_level.  The new interrupt level is effective when the
149 *  routine exits.
150 */
151#define _ISR_Set_level( _new_level ) \
152        _CPU_ISR_Set_level( _new_level )
153
154/**
155 *  This routine is the interrupt dispatcher.  ALL interrupts
156 *  are vectored to this routine so that minimal context can be saved
157 *  and setup performed before the application's high-level language
158 *  interrupt service routine is invoked.   After the application's
159 *  interrupt service routine returns control to this routine, it
160 *  will determine if a thread dispatch is necessary.  If so, it will
161 *  insure that the necessary thread scheduling operations are
162 *  performed when the outermost interrupt service routine exits.
163 *
164 *  @note  Implemented in assembly language.
165 */
166void _ISR_Handler( void );
167
168/**
169 *  This routine provides a wrapper so that the routine
170 *  @ref _Thread_Dispatch can be invoked when a reschedule is necessary
171 *  at the end of the outermost interrupt service routine.  This
172 *  wrapper is necessary to establish the processor context needed
173 *  by _Thread_Dispatch and to save the processor context which is
174 *  corrupted by _Thread_Dispatch.  This context typically consists
175 *  of registers which are not preserved across routine invocations.
176 *
177 *  @note  Implemented in assembly language.
178 */
179void _ISR_Dispatch( void );
180
181/**
182 *  This function returns TRUE if the processor is currently servicing
183 *  and interrupt and FALSE otherwise.   A return value of TRUE indicates
184 *  that the caller is an interrupt service routine, NOT a thread.  The
185 */
186#if (CPU_PROVIDES_ISR_IS_IN_PROGRESS == TRUE)
187boolean _ISR_Is_in_progress( void );
188#else
189#define _ISR_Is_in_progress() \
190        (_ISR_Nest_level != 0)
191#endif
192
193#include <rtems/score/isr.inl>
194
195#ifdef __cplusplus
196}
197#endif
198
199/**@}*/
200
201#endif
202/* end of include file */
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