1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Atomic Operations CPU API |
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5 | */ |
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6 | |
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7 | /* |
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8 | * COPYRIGHT (c) 2013 Deng Hengyi. |
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9 | * Copyright (c) 2015 embedded brains GmbH. |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.org/license/LICENSE. |
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14 | */ |
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15 | |
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16 | #ifndef _RTEMS_SCORE_CPUSTDATOMIC_H |
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17 | #define _RTEMS_SCORE_CPUSTDATOMIC_H |
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18 | |
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19 | #include <rtems/score/basedefs.h> |
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20 | |
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21 | #ifdef RTEMS_SMP |
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22 | #if defined(__cplusplus) && __GNUC__ >= 4 && __GNUC_MINOR__ >= 9 |
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23 | /* |
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24 | * The GCC 4.9 ships its own <stdatomic.h> which is not C++ compatible. The |
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25 | * suggested solution was to include <atomic> in case C++ is used. This works |
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26 | * at least with GCC 4.9. See also: |
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27 | * |
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28 | * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60932 |
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29 | * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=60940 |
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30 | */ |
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31 | #include <atomic> |
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32 | #define _RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC |
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33 | #else |
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34 | #include <stdatomic.h> |
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35 | #define _RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC |
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36 | #endif |
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37 | #else |
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38 | #include <rtems/score/isrlevel.h> |
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39 | #endif |
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40 | |
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41 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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42 | |
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43 | typedef std::atomic_uint CPU_atomic_Uint; |
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44 | |
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45 | typedef std::atomic_ulong CPU_atomic_Ulong; |
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46 | |
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47 | typedef std::atomic_uintptr_t CPU_atomic_Pointer; |
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48 | |
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49 | typedef std::atomic_flag CPU_atomic_Flag; |
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50 | |
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51 | typedef std::memory_order CPU_atomic_Order; |
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52 | |
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53 | #define CPU_ATOMIC_ORDER_RELAXED std::memory_order_relaxed |
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54 | |
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55 | #define CPU_ATOMIC_ORDER_ACQUIRE std::memory_order_acquire |
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56 | |
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57 | #define CPU_ATOMIC_ORDER_RELEASE std::memory_order_release |
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58 | |
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59 | #define CPU_ATOMIC_ORDER_ACQ_REL std::memory_order_acq_rel |
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60 | |
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61 | #define CPU_ATOMIC_ORDER_SEQ_CST std::memory_order_seq_cst |
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62 | |
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63 | #define CPU_ATOMIC_INITIALIZER_UINT( value ) ATOMIC_VAR_INIT( value ) |
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64 | |
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65 | #define CPU_ATOMIC_INITIALIZER_ULONG( value ) ATOMIC_VAR_INIT( value ) |
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66 | |
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67 | #define CPU_ATOMIC_INITIALIZER_PTR( value ) \ |
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68 | ATOMIC_VAR_INIT( (uintptr_t) (value) ) |
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69 | |
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70 | #define CPU_ATOMIC_INITIALIZER_FLAG ATOMIC_FLAG_INIT |
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71 | |
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72 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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73 | |
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74 | typedef atomic_uint CPU_atomic_Uint; |
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75 | |
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76 | typedef atomic_ulong CPU_atomic_Ulong; |
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77 | |
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78 | typedef atomic_uintptr_t CPU_atomic_Pointer; |
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79 | |
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80 | typedef atomic_flag CPU_atomic_Flag; |
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81 | |
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82 | typedef memory_order CPU_atomic_Order; |
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83 | |
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84 | #define CPU_ATOMIC_ORDER_RELAXED memory_order_relaxed |
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85 | |
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86 | #define CPU_ATOMIC_ORDER_ACQUIRE memory_order_acquire |
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87 | |
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88 | #define CPU_ATOMIC_ORDER_RELEASE memory_order_release |
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89 | |
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90 | #define CPU_ATOMIC_ORDER_ACQ_REL memory_order_acq_rel |
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91 | |
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92 | #define CPU_ATOMIC_ORDER_SEQ_CST memory_order_seq_cst |
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93 | |
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94 | #define CPU_ATOMIC_INITIALIZER_UINT( value ) ATOMIC_VAR_INIT( value ) |
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95 | |
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96 | #define CPU_ATOMIC_INITIALIZER_ULONG( value ) ATOMIC_VAR_INIT( value ) |
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97 | |
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98 | #define CPU_ATOMIC_INITIALIZER_PTR( value ) \ |
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99 | ATOMIC_VAR_INIT( (uintptr_t) (value) ) |
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100 | |
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101 | #define CPU_ATOMIC_INITIALIZER_FLAG ATOMIC_FLAG_INIT |
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102 | |
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103 | #else |
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104 | |
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105 | typedef unsigned int CPU_atomic_Uint; |
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106 | |
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107 | typedef unsigned long CPU_atomic_Ulong; |
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108 | |
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109 | typedef uintptr_t CPU_atomic_Pointer; |
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110 | |
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111 | typedef bool CPU_atomic_Flag; |
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112 | |
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113 | typedef int CPU_atomic_Order; |
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114 | |
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115 | #define CPU_ATOMIC_ORDER_RELAXED 0 |
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116 | |
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117 | #define CPU_ATOMIC_ORDER_ACQUIRE 2 |
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118 | |
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119 | #define CPU_ATOMIC_ORDER_RELEASE 3 |
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120 | |
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121 | #define CPU_ATOMIC_ORDER_ACQ_REL 4 |
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122 | |
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123 | #define CPU_ATOMIC_ORDER_SEQ_CST 5 |
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124 | |
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125 | #define CPU_ATOMIC_INITIALIZER_UINT( value ) ( value ) |
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126 | |
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127 | #define CPU_ATOMIC_INITIALIZER_ULONG( value ) ( value ) |
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128 | |
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129 | #define CPU_ATOMIC_INITIALIZER_PTR( value ) ( (uintptr_t) (value) ) |
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130 | |
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131 | #define CPU_ATOMIC_INITIALIZER_FLAG false |
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132 | |
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133 | #endif |
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134 | |
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135 | static inline void _CPU_atomic_Fence( CPU_atomic_Order order ) |
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136 | { |
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137 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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138 | std::atomic_thread_fence( order ); |
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139 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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140 | atomic_thread_fence( order ); |
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141 | #else |
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142 | (void) order; |
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143 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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144 | #endif |
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145 | } |
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146 | |
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147 | static inline void _CPU_atomic_Init_uint( CPU_atomic_Uint *obj, unsigned int desired ) |
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148 | { |
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149 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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150 | obj->store( desired ); |
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151 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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152 | atomic_init( obj, desired ); |
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153 | #else |
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154 | *obj = desired; |
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155 | #endif |
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156 | } |
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157 | |
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158 | static inline void _CPU_atomic_Init_ulong( CPU_atomic_Ulong *obj, unsigned long desired ) |
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159 | { |
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160 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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161 | obj->store( desired ); |
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162 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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163 | atomic_init( obj, desired ); |
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164 | #else |
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165 | *obj = desired; |
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166 | #endif |
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167 | } |
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168 | |
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169 | static inline void _CPU_atomic_Init_ptr( CPU_atomic_Pointer *obj, void *desired ) |
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170 | { |
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171 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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172 | obj->store( (uintptr_t) desired ); |
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173 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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174 | atomic_init( obj, (uintptr_t) desired ); |
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175 | #else |
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176 | *obj = (uintptr_t) desired; |
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177 | #endif |
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178 | } |
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179 | |
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180 | static inline unsigned int _CPU_atomic_Load_uint( const CPU_atomic_Uint *obj, CPU_atomic_Order order ) |
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181 | { |
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182 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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183 | return obj->load( order ); |
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184 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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185 | return atomic_load_explicit( obj, order ); |
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186 | #else |
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187 | (void) order; |
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188 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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189 | return *obj; |
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190 | #endif |
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191 | } |
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192 | |
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193 | static inline unsigned long _CPU_atomic_Load_ulong( const CPU_atomic_Ulong *obj, CPU_atomic_Order order ) |
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194 | { |
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195 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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196 | return obj->load( order ); |
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197 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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198 | return atomic_load_explicit( obj, order ); |
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199 | #else |
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200 | (void) order; |
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201 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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202 | return *obj; |
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203 | #endif |
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204 | } |
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205 | |
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206 | static inline void *_CPU_atomic_Load_ptr( const CPU_atomic_Pointer *obj, CPU_atomic_Order order ) |
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207 | { |
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208 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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209 | return (void *) obj->load( order ); |
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210 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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211 | return (void *) atomic_load_explicit( obj, order ); |
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212 | #else |
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213 | (void) order; |
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214 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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215 | return (void *) *obj; |
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216 | #endif |
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217 | } |
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218 | |
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219 | static inline void _CPU_atomic_Store_uint( CPU_atomic_Uint *obj, unsigned int desired, CPU_atomic_Order order ) |
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220 | { |
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221 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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222 | obj->store( desired ); |
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223 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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224 | atomic_store_explicit( obj, desired, order ); |
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225 | #else |
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226 | (void) order; |
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227 | *obj = desired; |
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228 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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229 | #endif |
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230 | } |
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231 | |
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232 | static inline void _CPU_atomic_Store_ulong( CPU_atomic_Ulong *obj, unsigned long desired, CPU_atomic_Order order ) |
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233 | { |
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234 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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235 | obj->store( desired ); |
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236 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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237 | atomic_store_explicit( obj, desired, order ); |
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238 | #else |
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239 | (void) order; |
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240 | *obj = desired; |
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241 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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242 | #endif |
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243 | } |
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244 | |
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245 | static inline void _CPU_atomic_Store_ptr( CPU_atomic_Pointer *obj, void *desired, CPU_atomic_Order order ) |
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246 | { |
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247 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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248 | obj->store( (uintptr_t) desired ); |
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249 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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250 | atomic_store_explicit( obj, (uintptr_t) desired, order ); |
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251 | #else |
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252 | (void) order; |
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253 | *obj = (uintptr_t) desired; |
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254 | RTEMS_COMPILER_MEMORY_BARRIER(); |
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255 | #endif |
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256 | } |
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257 | |
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258 | static inline unsigned int _CPU_atomic_Fetch_add_uint( CPU_atomic_Uint *obj, unsigned int arg, CPU_atomic_Order order ) |
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259 | { |
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260 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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261 | return obj->fetch_add( arg, order ); |
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262 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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263 | return atomic_fetch_add_explicit( obj, arg, order ); |
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264 | #else |
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265 | unsigned int val; |
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266 | ISR_Level level; |
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267 | |
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268 | (void) order; |
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269 | _ISR_Disable( level ); |
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270 | val = *obj; |
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271 | *obj = val + arg; |
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272 | _ISR_Enable( level ); |
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273 | |
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274 | return val; |
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275 | #endif |
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276 | } |
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277 | |
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278 | static inline unsigned long _CPU_atomic_Fetch_add_ulong( CPU_atomic_Ulong *obj, unsigned long arg, CPU_atomic_Order order ) |
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279 | { |
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280 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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281 | return obj->fetch_add( arg, order ); |
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282 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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283 | return atomic_fetch_add_explicit( obj, arg, order ); |
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284 | #else |
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285 | unsigned long val; |
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286 | ISR_Level level; |
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287 | |
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288 | (void) order; |
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289 | _ISR_Disable( level ); |
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290 | val = *obj; |
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291 | *obj = val + arg; |
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292 | _ISR_Enable( level ); |
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293 | |
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294 | return val; |
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295 | #endif |
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296 | } |
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297 | |
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298 | static inline void *_CPU_atomic_Fetch_add_ptr( CPU_atomic_Pointer *obj, void *arg, CPU_atomic_Order order ) |
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299 | { |
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300 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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301 | return (void *) obj->fetch_add( (uintptr_t) arg, order ); |
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302 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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303 | return (void *) atomic_fetch_add_explicit( obj, (uintptr_t) arg, order ); |
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304 | #else |
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305 | uintptr_t val; |
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306 | ISR_Level level; |
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307 | |
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308 | (void) order; |
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309 | _ISR_Disable( level ); |
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310 | val = *obj; |
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311 | *obj = val + (uintptr_t) arg; |
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312 | _ISR_Enable( level ); |
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313 | |
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314 | return (void *) val; |
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315 | #endif |
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316 | } |
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317 | |
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318 | static inline unsigned int _CPU_atomic_Fetch_sub_uint( CPU_atomic_Uint *obj, unsigned int arg, CPU_atomic_Order order ) |
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319 | { |
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320 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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321 | return obj->fetch_sub( arg, order ); |
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322 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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323 | return atomic_fetch_sub_explicit( obj, arg, order ); |
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324 | #else |
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325 | unsigned int val; |
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326 | ISR_Level level; |
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327 | |
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328 | (void) order; |
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329 | _ISR_Disable( level ); |
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330 | val = *obj; |
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331 | *obj = val - arg; |
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332 | _ISR_Enable( level ); |
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333 | |
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334 | return val; |
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335 | #endif |
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336 | } |
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337 | |
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338 | static inline unsigned long _CPU_atomic_Fetch_sub_ulong( CPU_atomic_Ulong *obj, unsigned long arg, CPU_atomic_Order order ) |
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339 | { |
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340 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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341 | return obj->fetch_sub( arg, order ); |
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342 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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343 | return atomic_fetch_sub_explicit( obj, arg, order ); |
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344 | #else |
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345 | unsigned long val; |
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346 | ISR_Level level; |
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347 | |
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348 | (void) order; |
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349 | _ISR_Disable( level ); |
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350 | val = *obj; |
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351 | *obj = val - arg; |
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352 | _ISR_Enable( level ); |
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353 | |
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354 | return val; |
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355 | #endif |
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356 | } |
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357 | |
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358 | static inline void *_CPU_atomic_Fetch_sub_ptr( CPU_atomic_Pointer *obj, void *arg, CPU_atomic_Order order ) |
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359 | { |
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360 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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361 | return (void *) obj->fetch_sub( (uintptr_t) arg, order ); |
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362 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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363 | return (void *) atomic_fetch_sub_explicit( obj, (uintptr_t) arg, order ); |
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364 | #else |
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365 | uintptr_t val; |
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366 | ISR_Level level; |
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367 | |
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368 | (void) order; |
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369 | _ISR_Disable( level ); |
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370 | val = *obj; |
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371 | *obj = val - (uintptr_t) arg; |
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372 | _ISR_Enable( level ); |
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373 | |
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374 | return (void *) val; |
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375 | #endif |
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376 | } |
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377 | |
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378 | static inline unsigned int _CPU_atomic_Fetch_or_uint( CPU_atomic_Uint *obj, unsigned int arg, CPU_atomic_Order order ) |
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379 | { |
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380 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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381 | return obj->fetch_or( arg, order ); |
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382 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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383 | return atomic_fetch_or_explicit( obj, arg, order ); |
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384 | #else |
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385 | unsigned int val; |
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386 | ISR_Level level; |
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387 | |
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388 | (void) order; |
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389 | _ISR_Disable( level ); |
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390 | val = *obj; |
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391 | *obj = val | arg; |
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392 | _ISR_Enable( level ); |
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393 | |
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394 | return val; |
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395 | #endif |
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396 | } |
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397 | |
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398 | static inline unsigned long _CPU_atomic_Fetch_or_ulong( CPU_atomic_Ulong *obj, unsigned long arg, CPU_atomic_Order order ) |
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399 | { |
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400 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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401 | return obj->fetch_or( arg, order ); |
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402 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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403 | return atomic_fetch_or_explicit( obj, arg, order ); |
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404 | #else |
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405 | unsigned long val; |
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406 | ISR_Level level; |
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407 | |
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408 | (void) order; |
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409 | _ISR_Disable( level ); |
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410 | val = *obj; |
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411 | *obj = val | arg; |
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412 | _ISR_Enable( level ); |
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413 | |
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414 | return val; |
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415 | #endif |
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416 | } |
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417 | |
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418 | static inline void *_CPU_atomic_Fetch_or_ptr( CPU_atomic_Pointer *obj, void *arg, CPU_atomic_Order order ) |
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419 | { |
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420 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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421 | return (void *) obj->fetch_or( (uintptr_t) arg, order ); |
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422 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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423 | return (void *) atomic_fetch_or_explicit( obj, (uintptr_t) arg, order ); |
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424 | #else |
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425 | uintptr_t val; |
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426 | ISR_Level level; |
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427 | |
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428 | (void) order; |
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429 | _ISR_Disable( level ); |
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430 | val = *obj; |
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431 | *obj = val | (uintptr_t) arg; |
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432 | _ISR_Enable( level ); |
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433 | |
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434 | return (void *) val; |
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435 | #endif |
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436 | } |
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437 | |
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438 | static inline unsigned int _CPU_atomic_Fetch_and_uint( CPU_atomic_Uint *obj, unsigned int arg, CPU_atomic_Order order ) |
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439 | { |
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440 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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441 | return obj->fetch_and( arg, order ); |
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442 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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443 | return atomic_fetch_and_explicit( obj, arg, order ); |
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444 | #else |
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445 | unsigned int val; |
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446 | ISR_Level level; |
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447 | |
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448 | (void) order; |
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449 | _ISR_Disable( level ); |
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450 | val = *obj; |
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451 | *obj = val & arg; |
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452 | _ISR_Enable( level ); |
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453 | |
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454 | return val; |
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455 | #endif |
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456 | } |
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457 | |
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458 | static inline unsigned long _CPU_atomic_Fetch_and_ulong( CPU_atomic_Ulong *obj, unsigned long arg, CPU_atomic_Order order ) |
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459 | { |
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460 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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461 | return obj->fetch_and( arg, order ); |
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462 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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463 | return atomic_fetch_and_explicit( obj, arg, order ); |
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464 | #else |
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465 | unsigned long val; |
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466 | ISR_Level level; |
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467 | |
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468 | (void) order; |
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469 | _ISR_Disable( level ); |
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470 | val = *obj; |
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471 | *obj = val & arg; |
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472 | _ISR_Enable( level ); |
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473 | |
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474 | return val; |
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475 | #endif |
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476 | } |
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477 | |
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478 | static inline void *_CPU_atomic_Fetch_and_ptr( CPU_atomic_Pointer *obj, void *arg, CPU_atomic_Order order ) |
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479 | { |
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480 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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481 | return (void *) obj->fetch_and( (uintptr_t) arg, order ); |
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482 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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483 | return (void *) atomic_fetch_and_explicit( obj, (uintptr_t) arg, order ); |
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484 | #else |
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485 | uintptr_t val; |
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486 | ISR_Level level; |
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487 | |
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488 | (void) order; |
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489 | _ISR_Disable( level ); |
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490 | val = *obj; |
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491 | *obj = val & (uintptr_t) arg; |
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492 | _ISR_Enable( level ); |
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493 | |
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494 | return (void *) val; |
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495 | #endif |
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496 | } |
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497 | |
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498 | static inline unsigned int _CPU_atomic_Exchange_uint( CPU_atomic_Uint *obj, unsigned int desired, CPU_atomic_Order order ) |
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499 | { |
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500 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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501 | return obj->exchange( desired, order ); |
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502 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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503 | return atomic_exchange_explicit( obj, desired, order ); |
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504 | #else |
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505 | unsigned int val; |
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506 | ISR_Level level; |
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507 | |
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508 | (void) order; |
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509 | _ISR_Disable( level ); |
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510 | val = *obj; |
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511 | *obj = desired; |
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512 | _ISR_Enable( level ); |
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513 | |
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514 | return val; |
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515 | #endif |
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516 | } |
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517 | |
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518 | static inline unsigned long _CPU_atomic_Exchange_ulong( CPU_atomic_Ulong *obj, unsigned long desired, CPU_atomic_Order order ) |
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519 | { |
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520 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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521 | return obj->exchange( desired, order ); |
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522 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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523 | return atomic_exchange_explicit( obj, desired, order ); |
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524 | #else |
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525 | unsigned long val; |
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526 | ISR_Level level; |
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527 | |
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528 | (void) order; |
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529 | _ISR_Disable( level ); |
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530 | val = *obj; |
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531 | *obj = desired; |
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532 | _ISR_Enable( level ); |
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533 | |
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534 | return val; |
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535 | #endif |
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536 | } |
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537 | |
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538 | static inline void *_CPU_atomic_Exchange_ptr( CPU_atomic_Pointer *obj, void *desired, CPU_atomic_Order order ) |
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539 | { |
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540 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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541 | return (void *) obj->exchange( (uintptr_t) desired, order ); |
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542 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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543 | return (void *) atomic_exchange_explicit( obj, (uintptr_t) desired, order ); |
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544 | #else |
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545 | uintptr_t val; |
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546 | ISR_Level level; |
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547 | |
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548 | (void) order; |
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549 | _ISR_Disable( level ); |
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550 | val = *obj; |
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551 | *obj = (uintptr_t) desired; |
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552 | _ISR_Enable( level ); |
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553 | |
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554 | return (void *) val; |
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555 | #endif |
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556 | } |
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557 | |
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558 | static inline bool _CPU_atomic_Compare_exchange_uint( CPU_atomic_Uint *obj, unsigned int *expected, unsigned int desired, CPU_atomic_Order succ, CPU_atomic_Order fail ) |
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559 | { |
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560 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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561 | return obj->compare_exchange_strong( *expected, desired, succ, fail ); |
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562 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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563 | return atomic_compare_exchange_strong_explicit( obj, expected, desired, succ, fail ); |
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564 | #else |
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565 | bool success; |
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566 | ISR_Level level; |
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567 | |
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568 | (void) succ; |
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569 | (void) fail; |
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570 | _ISR_Disable( level ); |
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571 | success = *obj == *expected; |
---|
572 | if ( success ) { |
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573 | *obj = desired; |
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574 | } |
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575 | _ISR_Enable( level ); |
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576 | |
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577 | return success; |
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578 | #endif |
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579 | } |
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580 | |
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581 | static inline bool _CPU_atomic_Compare_exchange_ulong( CPU_atomic_Ulong *obj, unsigned long *expected, unsigned long desired, CPU_atomic_Order succ, CPU_atomic_Order fail ) |
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582 | { |
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583 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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584 | return obj->compare_exchange_strong( *expected, desired, succ, fail ); |
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585 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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586 | return atomic_compare_exchange_strong_explicit( obj, expected, desired, succ, fail ); |
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587 | #else |
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588 | bool success; |
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589 | ISR_Level level; |
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590 | |
---|
591 | (void) succ; |
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592 | (void) fail; |
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593 | _ISR_Disable( level ); |
---|
594 | success = *obj == *expected; |
---|
595 | if ( success ) { |
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596 | *obj = desired; |
---|
597 | } |
---|
598 | _ISR_Enable( level ); |
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599 | |
---|
600 | return success; |
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601 | #endif |
---|
602 | } |
---|
603 | |
---|
604 | static inline bool _CPU_atomic_Compare_exchange_ptr( CPU_atomic_Pointer *obj, void **expected, void *desired, CPU_atomic_Order succ, CPU_atomic_Order fail ) |
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605 | { |
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606 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
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607 | return obj->compare_exchange_strong( *(uintptr_t *) expected, (uintptr_t) desired, succ, fail ); |
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608 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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609 | return atomic_compare_exchange_strong_explicit( obj, (uintptr_t *) expected, (uintptr_t) desired, succ, fail ); |
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610 | #else |
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611 | bool success; |
---|
612 | ISR_Level level; |
---|
613 | |
---|
614 | (void) succ; |
---|
615 | (void) fail; |
---|
616 | _ISR_Disable( level ); |
---|
617 | success = *obj == (uintptr_t) *expected; |
---|
618 | if ( success ) { |
---|
619 | *obj = (uintptr_t) desired; |
---|
620 | } |
---|
621 | _ISR_Enable( level ); |
---|
622 | |
---|
623 | return success; |
---|
624 | #endif |
---|
625 | } |
---|
626 | |
---|
627 | static inline void _CPU_atomic_Flag_clear( CPU_atomic_Flag *obj, CPU_atomic_Order order ) |
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628 | { |
---|
629 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
---|
630 | obj->clear( order ); |
---|
631 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
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632 | atomic_flag_clear_explicit( obj, order ); |
---|
633 | #else |
---|
634 | (void) order; |
---|
635 | *obj = false; |
---|
636 | #endif |
---|
637 | } |
---|
638 | |
---|
639 | static inline bool _CPU_atomic_Flag_test_and_set( CPU_atomic_Flag *obj, CPU_atomic_Order order ) |
---|
640 | { |
---|
641 | #if defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_ATOMIC) |
---|
642 | return obj->test_and_set( order ); |
---|
643 | #elif defined(_RTEMS_SCORE_CPUSTDATOMIC_USE_STDATOMIC) |
---|
644 | return atomic_flag_test_and_set_explicit( obj, order ); |
---|
645 | #else |
---|
646 | bool flag; |
---|
647 | ISR_Level level; |
---|
648 | |
---|
649 | (void) order; |
---|
650 | _ISR_Disable( level ); |
---|
651 | flag = *obj; |
---|
652 | *obj = true; |
---|
653 | _ISR_Enable( level ); |
---|
654 | |
---|
655 | return flag; |
---|
656 | #endif |
---|
657 | } |
---|
658 | |
---|
659 | #endif /* _RTEMS_SCORE_CPUSTDATOMIC_H */ |
---|