1 | /* |
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2 | * Copyright (c) 2018. |
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3 | * Amaan Cheval <amaan.cheval@gmail.com> |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * |
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14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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24 | * SUCH DAMAGE. |
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25 | */ |
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26 | |
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27 | #ifdef HAVE_CONFIG_H |
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28 | #include "config.h" |
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29 | #endif |
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30 | |
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31 | #include <rtems/asm.h> |
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32 | #include <rtems/score/cpu.h> |
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33 | |
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34 | #ifndef CPU_STACK_ALIGNMENT |
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35 | #error "Missing header? CPU_STACK_ALIGNMENT not defined" |
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36 | #endif |
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37 | |
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38 | BEGIN_CODE |
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39 | |
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40 | /* |
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41 | * void _CPU_Context_switch( run_context, heir_context ) |
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42 | * |
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43 | * This routine performs a normal non-FP context. |
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44 | */ |
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45 | |
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46 | .p2align 1 |
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47 | PUBLIC(_CPU_Context_switch) |
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48 | |
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49 | /* save context argument */ |
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50 | .set RUNCONTEXT_ARG, REG_ARG0 |
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51 | /* restore context argument */ |
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52 | .set HEIRCONTEXT_ARG, REG_ARG1 |
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53 | |
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54 | SYM(_CPU_Context_switch): |
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55 | movq RUNCONTEXT_ARG, rax /* rax = running threads context */ |
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56 | |
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57 | /* Fill up Context_Control struct */ |
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58 | pushf |
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59 | popq (0 * CPU_SIZEOF_POINTER)(rax) /* pop rflags into context */ |
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60 | movq rbx, (1 * CPU_SIZEOF_POINTER)(rax) |
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61 | movq rsp, (2 * CPU_SIZEOF_POINTER)(rax) |
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62 | movq rbp, (3 * CPU_SIZEOF_POINTER)(rax) |
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63 | movq r12, (4 * CPU_SIZEOF_POINTER)(rax) |
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64 | movq r13, (5 * CPU_SIZEOF_POINTER)(rax) |
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65 | movq r14, (6 * CPU_SIZEOF_POINTER)(rax) |
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66 | movq r15, (7 * CPU_SIZEOF_POINTER)(rax) |
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67 | |
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68 | movq HEIRCONTEXT_ARG, rax /* rax = heir threads context */ |
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69 | |
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70 | restore: |
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71 | pushq (0 * CPU_SIZEOF_POINTER)(rax) /* push rflags */ |
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72 | popf /* restore rflags */ |
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73 | movq (1 * CPU_SIZEOF_POINTER)(rax), rbx |
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74 | movq (2 * CPU_SIZEOF_POINTER)(rax), rsp |
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75 | movq (3 * CPU_SIZEOF_POINTER)(rax), rbp |
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76 | movq (4 * CPU_SIZEOF_POINTER)(rax), r12 |
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77 | movq (5 * CPU_SIZEOF_POINTER)(rax), r13 |
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78 | movq (6 * CPU_SIZEOF_POINTER)(rax), r14 |
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79 | movq (7 * CPU_SIZEOF_POINTER)(rax), r15 |
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80 | |
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81 | /* XXX: TLS - load GDT and refresh FS segment selector */ |
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82 | |
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83 | ret |
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84 | |
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85 | /* |
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86 | * void _CPU_Context_restore( new_context ) |
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87 | * |
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88 | * This routine performs a normal non-FP context restore. |
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89 | */ |
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90 | |
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91 | PUBLIC(_CPU_Context_restore) |
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92 | |
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93 | .set NEWCONTEXT_ARG, REG_ARG0 /* context to restore argument */ |
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94 | |
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95 | SYM(_CPU_Context_restore): |
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96 | movq NEWCONTEXT_ARG, rax /* rax = running threads context */ |
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97 | jmp restore |
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98 | |
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99 | END_CODE |
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100 | END |
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