source: rtems/cpukit/score/cpu/x86_64/x86_64-context-switch.S @ 5c6edee

5
Last change on this file since 5c6edee was ab971bf5, checked in by Amaan Cheval <amaan.cheval@…>, on 08/13/18 at 10:21:47

bsps/x86_64: Reorganize header files and compile-options

Updates #2898.

  • Property mode set to 100644
File size: 3.3 KB
Line 
1/*
2 * Copyright (c) 2018.
3 * Amaan Cheval <amaan.cheval@gmail.com>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#ifdef HAVE_CONFIG_H
28#include "config.h"
29#endif
30
31#include <rtems/asm.h>
32#include <rtems/score/cpu.h>
33
34#ifndef CPU_STACK_ALIGNMENT
35#error "Missing header? CPU_STACK_ALIGNMENT not defined"
36#endif
37
38BEGIN_CODE
39
40/*
41 *  void _CPU_Context_switch( run_context, heir_context )
42 *
43 *  This routine performs a normal non-FP context.
44 */
45
46.p2align  1
47PUBLIC(_CPU_Context_switch)
48
49/* save context argument */
50.set RUNCONTEXT_ARG,   REG_ARG0
51/* restore context argument */
52.set HEIRCONTEXT_ARG,  REG_ARG1
53
54SYM(_CPU_Context_switch):
55  movq    RUNCONTEXT_ARG, rax  /* rax = running threads context */
56
57  /* Fill up Context_Control struct */
58  pushf
59  popq               (0 * CPU_SIZEOF_POINTER)(rax) /* pop rflags into context */
60  movq    rbx,       (1 * CPU_SIZEOF_POINTER)(rax)
61  movq    rsp,       (2 * CPU_SIZEOF_POINTER)(rax)
62  movq    rbp,       (3 * CPU_SIZEOF_POINTER)(rax)
63  movq    r12,       (4 * CPU_SIZEOF_POINTER)(rax)
64  movq    r13,       (5 * CPU_SIZEOF_POINTER)(rax)
65  movq    r14,       (6 * CPU_SIZEOF_POINTER)(rax)
66  movq    r15,       (7 * CPU_SIZEOF_POINTER)(rax)
67
68  movq    HEIRCONTEXT_ARG, rax /* rax = heir threads context */
69
70restore:
71  pushq (0 * CPU_SIZEOF_POINTER)(rax)       /* push rflags */
72  popf                                      /* restore rflags */
73  movq  (1 * CPU_SIZEOF_POINTER)(rax), rbx
74  movq  (2 * CPU_SIZEOF_POINTER)(rax), rsp
75  movq  (3 * CPU_SIZEOF_POINTER)(rax), rbp
76  movq  (4 * CPU_SIZEOF_POINTER)(rax), r12
77  movq  (5 * CPU_SIZEOF_POINTER)(rax), r13
78  movq  (6 * CPU_SIZEOF_POINTER)(rax), r14
79  movq  (7 * CPU_SIZEOF_POINTER)(rax), r15
80
81  /* XXX: TLS - load GDT and refresh FS segment selector */
82
83  ret
84
85/*
86 *  void _CPU_Context_restore( new_context )
87 *
88 *  This routine performs a normal non-FP context restore.
89 */
90
91PUBLIC(_CPU_Context_restore)
92
93.set NEWCONTEXT_ARG,   REG_ARG0       /* context to restore argument */
94
95SYM(_CPU_Context_restore):
96  movq      NEWCONTEXT_ARG, rax  /* rax = running threads context */
97  jmp       restore
98
99END_CODE
100END
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