1 | /* |
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2 | * Copyright (c) 2018. |
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3 | * Amaan Cheval <amaan.cheval@gmail.com> |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * |
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14 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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15 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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16 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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17 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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18 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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20 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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21 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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22 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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23 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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24 | * SUCH DAMAGE. |
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25 | */ |
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26 | |
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27 | #ifndef _RTEMS_SCORE_CPU_ASM_H |
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28 | #define _RTEMS_SCORE_CPU_ASM_H |
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29 | |
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30 | #if !ASM |
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31 | |
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32 | #include <rtems/score/basedefs.h> |
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33 | |
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34 | RTEMS_INLINE_ROUTINE uint8_t inport_byte(uint16_t port) |
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35 | { |
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36 | uint8_t ret; |
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37 | __asm__ volatile ( "inb %1, %0" |
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38 | : "=a" (ret) |
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39 | : "Nd" (port) ); |
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40 | return ret; |
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41 | } |
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42 | |
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43 | RTEMS_INLINE_ROUTINE void outport_byte(uint16_t port, uint8_t val) |
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44 | { |
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45 | __asm__ volatile ( "outb %0, %1" : : "a" (val), "Nd" (port) ); |
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46 | } |
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47 | |
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48 | RTEMS_INLINE_ROUTINE uint16_t amd64_get_cs(void) |
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49 | { |
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50 | uint16_t segment = 0; |
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51 | |
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52 | __asm__ volatile ( "movw %%cs, %0" : "=r" (segment) : "0" (segment) ); |
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53 | |
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54 | return segment; |
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55 | } |
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56 | |
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57 | RTEMS_INLINE_ROUTINE void amd64_set_cr3(uint64_t segment) |
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58 | { |
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59 | __asm__ volatile ( "movq %0, %%cr3" : "=r" (segment) : "0" (segment) ); |
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60 | } |
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61 | |
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62 | RTEMS_INLINE_ROUTINE void cpuid( |
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63 | uint32_t code, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx |
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64 | ) { |
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65 | __asm__ volatile ( "cpuid" |
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66 | : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx) |
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67 | : "a" (code) ); |
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68 | } |
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69 | |
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70 | RTEMS_INLINE_ROUTINE void amd64_enable_interrupts(void) |
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71 | { |
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72 | __asm__ volatile ( "sti" ); |
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73 | } |
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74 | |
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75 | RTEMS_INLINE_ROUTINE void amd64_disable_interrupts(void) |
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76 | { |
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77 | __asm__ volatile ( "cli" ); |
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78 | } |
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79 | #endif /* !ASM */ |
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80 | |
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81 | #endif |
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