source: rtems/cpukit/score/cpu/x86_64/include/rtems/score/cpu_asm.h @ 4544749e

5
Last change on this file since 4544749e was 4544749e, checked in by Amaan Cheval <amaan.cheval@…>, on 08/13/18 at 10:33:12

bsps/x86_64: Add paging support with 1GiB super pages

Updates #2898.

  • Property mode set to 100644
File size: 2.2 KB
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1/*
2 * Copyright (c) 2018.
3 * Amaan Cheval <amaan.cheval@gmail.com>
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#ifndef _RTEMS_SCORE_CPU_ASM_H
28#define _RTEMS_SCORE_CPU_ASM_H
29
30#if !ASM
31
32#include <rtems/score/basedefs.h>
33
34RTEMS_INLINE_ROUTINE uint8_t inport_byte(uint16_t port)
35{
36  uint8_t ret;
37  __asm__ volatile ( "inb %1, %0"
38                     : "=a" (ret)
39                     : "Nd" (port) );
40  return ret;
41}
42
43RTEMS_INLINE_ROUTINE void outport_byte(uint16_t port, uint8_t val)
44{
45  __asm__ volatile ( "outb %0, %1" : : "a" (val), "Nd" (port) );
46}
47
48
49RTEMS_INLINE_ROUTINE void amd64_set_cr3(uint64_t segment)
50{
51  __asm__ volatile ( "movq %0, %%cr3" : "=r" (segment) : "0" (segment) );
52}
53
54RTEMS_INLINE_ROUTINE void cpuid(
55  uint32_t code, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx
56) {
57  __asm__ volatile ( "cpuid"
58                     : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
59                     : "a" (code) );
60}
61#endif /* !ASM */
62
63#endif
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