1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief x86_64 Dependent Source |
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5 | * |
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6 | * This include file contains information pertaining to the x86_64 processor. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2018. |
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11 | * Amaan Cheval <amaan.cheval@gmail.com> |
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12 | * |
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13 | * Redistribution and use in source and binary forms, with or without |
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14 | * modification, are permitted provided that the following conditions |
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15 | * are met: |
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16 | * 1. Redistributions of source code must retain the above copyright |
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17 | * notice, this list of conditions and the following disclaimer. |
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18 | * 2. Redistributions in binary form must reproduce the above copyright |
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19 | * notice, this list of conditions and the following disclaimer in the |
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20 | * documentation and/or other materials provided with the distribution. |
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21 | * |
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22 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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23 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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25 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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28 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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29 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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30 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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31 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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32 | * SUCH DAMAGE. |
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33 | */ |
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34 | |
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35 | #ifndef _RTEMS_SCORE_CPU_H |
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36 | #define _RTEMS_SCORE_CPU_H |
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37 | |
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38 | #ifdef __cplusplus |
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39 | extern "C" { |
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40 | #endif |
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41 | |
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42 | #include <rtems/score/basedefs.h> |
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43 | #include <rtems/score/cpu_asm.h> |
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44 | #include <rtems/score/x86_64.h> |
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45 | |
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46 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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47 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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48 | #define CPU_HARDWARE_FP FALSE |
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49 | #define CPU_SOFTWARE_FP FALSE |
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50 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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51 | #define CPU_IDLE_TASK_IS_FP FALSE |
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52 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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53 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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54 | #define CPU_STACK_GROWS_UP FALSE |
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55 | |
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56 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED(64) |
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57 | #define CPU_CACHE_LINE_BYTES 64 |
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58 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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59 | #define CPU_MAXIMUM_PROCESSORS 32 |
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60 | |
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61 | #define CPU_EFLAGS_INTERRUPTS_ON 0x00003202 |
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62 | #define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002 |
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63 | |
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64 | #ifndef ASM |
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65 | |
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66 | typedef struct { |
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67 | uint64_t rflags; |
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68 | |
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69 | /** |
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70 | * Callee-saved registers as listed in the SysV ABI document: |
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71 | * https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI |
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72 | */ |
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73 | uint64_t rbx; |
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74 | void *rsp; |
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75 | void *rbp; |
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76 | uint64_t r12; |
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77 | uint64_t r13; |
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78 | uint64_t r14; |
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79 | uint64_t r15; |
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80 | |
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81 | // XXX: FS segment descriptor for TLS |
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82 | |
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83 | #ifdef RTEMS_SMP |
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84 | volatile bool is_executing; |
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85 | #endif |
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86 | } Context_Control; |
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87 | |
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88 | #define _CPU_Context_Get_SP( _context ) \ |
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89 | (_context)->rsp |
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90 | |
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91 | /* |
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92 | * Caller-saved registers for interrupt frames |
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93 | */ |
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94 | typedef struct { |
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95 | /** |
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96 | * @note: rdi is a caller-saved register too, but it's used in function calls |
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97 | * and is hence saved separately on the stack; |
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98 | * |
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99 | * @see DISTINCT_INTERRUPT_ENTRY |
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100 | * @see _ISR_Handler |
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101 | */ |
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102 | |
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103 | uint64_t rax; |
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104 | uint64_t rcx; |
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105 | uint64_t rdx; |
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106 | uint64_t rsi; |
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107 | uint64_t r8; |
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108 | uint64_t r9; |
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109 | uint64_t r10; |
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110 | uint64_t r11; |
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111 | |
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112 | /* |
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113 | * This holds the rsp just before _ISR_Handler is called; it's needed because |
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114 | * in the handler, we align the stack to make further calls, and we're not |
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115 | * sure how alignment may move the stack-pointer around, leaving no way to get |
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116 | * back to the stack, and therefore the interrupt frame. |
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117 | */ |
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118 | uint64_t saved_rsp; |
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119 | |
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120 | /* XXX: |
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121 | * - FS segment selector for TLS |
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122 | * - x87 status word? |
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123 | * - MMX? |
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124 | * - XMM? |
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125 | */ |
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126 | } CPU_Interrupt_frame; |
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127 | |
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128 | #endif /* !ASM */ |
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129 | |
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130 | #define CPU_INTERRUPT_FRAME_SIZE 72 |
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131 | |
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132 | /* |
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133 | * When SMP is enabled, percpuasm.c has a similar assert, but since we use the |
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134 | * interrupt frame regardless of SMP, we'll confirm it here. |
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135 | */ |
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136 | #ifndef ASM |
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137 | RTEMS_STATIC_ASSERT( |
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138 | sizeof(CPU_Interrupt_frame) == CPU_INTERRUPT_FRAME_SIZE, |
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139 | CPU_INTERRUPT_FRAME_SIZE |
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140 | ); |
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141 | #endif |
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142 | |
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143 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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144 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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145 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
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146 | #define CPU_SIZEOF_POINTER 8 |
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147 | #define CPU_ALIGNMENT 8 |
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148 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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149 | #define CPU_STACK_ALIGNMENT 16 |
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150 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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151 | |
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152 | /* |
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153 | * ISR handler macros |
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154 | */ |
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155 | |
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156 | #ifndef ASM |
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157 | |
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158 | #define _CPU_Initialize_vectors() |
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159 | |
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160 | #define _CPU_ISR_Enable(_level) \ |
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161 | { \ |
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162 | amd64_enable_interrupts(); \ |
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163 | _level = 0; \ |
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164 | (void) _level; /* Prevent -Wunused-but-set-variable */ \ |
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165 | } |
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166 | |
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167 | #define _CPU_ISR_Disable(_level) \ |
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168 | { \ |
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169 | amd64_enable_interrupts(); \ |
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170 | _level = 1; \ |
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171 | (void) _level; /* Prevent -Wunused-but-set-variable */ \ |
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172 | } |
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173 | |
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174 | #define _CPU_ISR_Flash(_level) \ |
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175 | { \ |
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176 | amd64_enable_interrupts(); \ |
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177 | amd64_disable_interrupts(); \ |
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178 | _level = 1; \ |
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179 | (void) _level; /* Prevent -Wunused-but-set-variable */ \ |
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180 | } |
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181 | |
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182 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled(uint32_t level) |
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183 | { |
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184 | return (level & EFLAGS_INTR_ENABLE) != 0; |
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185 | } |
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186 | |
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187 | RTEMS_INLINE_ROUTINE void _CPU_ISR_Set_level(uint32_t new_level) |
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188 | { |
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189 | if ( new_level ) { |
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190 | amd64_disable_interrupts(); |
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191 | } |
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192 | else { |
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193 | amd64_enable_interrupts(); |
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194 | } |
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195 | } |
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196 | |
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197 | RTEMS_INLINE_ROUTINE uint32_t _CPU_ISR_Get_level(void) |
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198 | { |
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199 | uint64_t rflags; |
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200 | |
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201 | __asm__ volatile ( "pushf; \ |
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202 | popq %0" |
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203 | : "=rm" (rflags) |
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204 | ); |
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205 | |
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206 | uint32_t level = (rflags & EFLAGS_INTR_ENABLE) ? 0 : 1; |
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207 | return level; |
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208 | } |
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209 | |
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210 | /* end of ISR handler macros */ |
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211 | |
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212 | /* Context handler macros */ |
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213 | #define _CPU_Context_Destroy( _the_thread, _the_context ) \ |
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214 | { \ |
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215 | } |
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216 | |
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217 | void _CPU_Context_Initialize( |
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218 | Context_Control *the_context, |
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219 | void *stack_area_begin, |
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220 | size_t stack_area_size, |
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221 | uint32_t new_level, |
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222 | void (*entry_point)( void ), |
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223 | bool is_fp, |
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224 | void *tls_area |
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225 | ); |
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226 | |
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227 | #define _CPU_Context_Restart_self( _the_context ) \ |
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228 | _CPU_Context_restore( (_the_context) ); |
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229 | |
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230 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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231 | { \ |
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232 | *(*(_destination)) = _CPU_Null_fp_context; \ |
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233 | } |
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234 | |
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235 | /* end of Context handler macros */ |
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236 | |
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237 | /* Fatal Error manager macros */ |
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238 | |
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239 | #define _CPU_Fatal_halt( _source, _error ) \ |
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240 | { \ |
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241 | } |
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242 | |
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243 | /* end of Fatal Error manager macros */ |
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244 | |
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245 | /* Bitfield handler macros */ |
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246 | |
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247 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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248 | |
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249 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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250 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
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251 | { \ |
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252 | (_output) = 0; /* do something to prevent warnings */ \ |
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253 | } |
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254 | #endif |
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255 | |
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256 | /* end of Bitfield handler macros */ |
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257 | |
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258 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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259 | #define _CPU_Priority_Mask( _bit_number ) \ |
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260 | ( 1 << (_bit_number) ) |
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261 | #endif |
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262 | |
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263 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
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264 | #define _CPU_Priority_bits_index( _priority ) \ |
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265 | (_priority) |
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266 | #endif |
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267 | |
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268 | /* end of Priority handler macros */ |
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269 | |
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270 | /* functions */ |
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271 | |
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272 | void _CPU_Initialize(void); |
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273 | |
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274 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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275 | |
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276 | void _CPU_Context_switch( |
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277 | Context_Control *run, |
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278 | Context_Control *heir |
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279 | ); |
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280 | |
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281 | void _CPU_Context_restore( |
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282 | Context_Control *new_context |
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283 | ) RTEMS_NO_RETURN; |
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284 | |
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285 | typedef struct { |
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286 | uint32_t processor_state_register; |
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287 | uint32_t integer_registers [1]; |
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288 | double float_registers [1]; |
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289 | } CPU_Exception_frame; |
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290 | |
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291 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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292 | |
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293 | static inline uint32_t CPU_swap_u32( |
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294 | uint32_t value |
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295 | ) |
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296 | { |
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297 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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298 | |
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299 | byte4 = (value >> 24) & 0xff; |
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300 | byte3 = (value >> 16) & 0xff; |
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301 | byte2 = (value >> 8) & 0xff; |
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302 | byte1 = value & 0xff; |
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303 | |
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304 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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305 | return swapped; |
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306 | } |
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307 | |
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308 | #define CPU_swap_u16( value ) \ |
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309 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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310 | |
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311 | typedef uint32_t CPU_Counter_ticks; |
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312 | |
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313 | uint32_t _CPU_Counter_frequency( void ); |
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314 | |
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315 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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316 | |
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317 | |
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318 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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319 | CPU_Counter_ticks second, |
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320 | CPU_Counter_ticks first |
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321 | ) |
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322 | { |
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323 | return second - first; |
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324 | } |
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325 | |
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326 | #ifdef RTEMS_SMP |
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327 | * |
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328 | uint32_t _CPU_SMP_Initialize( void ); |
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329 | |
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330 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
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331 | |
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332 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
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333 | |
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334 | void _CPU_SMP_Prepare_start_multitasking( void ); |
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335 | |
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336 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
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337 | { |
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338 | return 123; |
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339 | } |
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340 | |
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341 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
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342 | |
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343 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
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344 | { |
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345 | __asm__ volatile ( "" : : : "memory" ); |
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346 | } |
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347 | |
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348 | static inline void _CPU_SMP_Processor_event_receive( void ) |
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349 | { |
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350 | __asm__ volatile ( "" : : : "memory" ); |
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351 | } |
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352 | |
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353 | static inline bool _CPU_Context_Get_is_executing( |
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354 | const Context_Control *context |
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355 | ) |
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356 | return context->is_executing; |
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357 | } |
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358 | |
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359 | static inline void _CPU_Context_Set_is_executing( |
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360 | Context_Control *context, |
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361 | bool is_executing |
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362 | ) |
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363 | { |
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364 | } |
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365 | |
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366 | #endif /* RTEMS_SMP */ |
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367 | |
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368 | typedef uintptr_t CPU_Uint32ptr; |
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369 | |
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370 | #ifdef __cplusplus |
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371 | } |
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372 | #endif |
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373 | |
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374 | #endif /* ASM */ |
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375 | |
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376 | #endif /* _RTEMS_SCORE_CPU_H */ |
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