source: rtems/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h @ ab971bf5

5
Last change on this file since ab971bf5 was ab971bf5, checked in by Amaan Cheval <amaan.cheval@…>, on 08/13/18 at 10:21:47

bsps/x86_64: Reorganize header files and compile-options

Updates #2898.

  • Property mode set to 100644
File size: 7.9 KB
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1/**
2 * @file rtems/score/cpu.h
3 *
4 * @brief x86_64 Dependent Source
5 *
6 * This include file contains information pertaining to the x86_64 processor.
7 */
8
9/*
10 * Copyright (c) 2018.
11 * Amaan Cheval <amaan.cheval@gmail.com>
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#ifndef _RTEMS_SCORE_CPU_H
36#define _RTEMS_SCORE_CPU_H
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <rtems/score/basedefs.h>
43#include <rtems/score/cpu_asm.h>
44#include <rtems/score/x86_64.h>
45
46#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
47#define CPU_ISR_PASSES_FRAME_POINTER FALSE
48// XXX: Enable FPU support
49#define CPU_HARDWARE_FP     FALSE
50#define CPU_SOFTWARE_FP     FALSE
51#define CPU_ALL_TASKS_ARE_FP     FALSE
52#define CPU_IDLE_TASK_IS_FP      FALSE
53#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
54#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
55#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
56#define CPU_STACK_GROWS_UP               FALSE
57
58#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED(64)
59#define CPU_CACHE_LINE_BYTES 64
60#define CPU_MODES_INTERRUPT_MASK   0x00000001
61#define CPU_MAXIMUM_PROCESSORS 32
62
63#define CPU_EFLAGS_INTERRUPTS_ON  0x00003202
64#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
65
66#ifndef ASM
67
68typedef struct {
69  uint64_t rflags;
70
71  /**
72   * Callee-saved registers as listed in the SysV ABI document:
73   * https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI
74   */
75  uint64_t rbx;
76  void    *rsp;
77  void    *rbp;
78  uint64_t r12;
79  uint64_t r13;
80  uint64_t r14;
81  uint64_t r15;
82
83  // XXX: FS segment descriptor for TLS
84
85#ifdef RTEMS_SMP
86    volatile bool is_executing;
87#endif
88} Context_Control;
89
90#define _CPU_Context_Get_SP( _context ) \
91  (_context)->rsp
92
93typedef struct {
94  /* XXX: MMX, XMM, others?
95   *
96   * All x87 registers are caller-saved, so callees that make use of the MMX
97   * registers may use the faster femms instruction
98   */
99
100  /** FPU registers are listed here */
101  double      some_float_register;
102} Context_Control_fp;
103
104typedef struct {
105    uint32_t   special_interrupt_register;
106} CPU_Interrupt_frame;
107
108#endif /* !ASM */
109
110
111#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
112#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
113#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
114#define CPU_STACK_MINIMUM_SIZE          (1024*4)
115#define CPU_SIZEOF_POINTER         8
116#define CPU_ALIGNMENT              8
117#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
118#define CPU_STACK_ALIGNMENT        16
119#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
120
121/*
122 *  ISR handler macros
123 */
124
125#ifndef ASM
126
127#define _CPU_Initialize_vectors()
128
129// XXX: For RTEMS critical sections
130#define _CPU_ISR_Disable( _isr_cookie ) \
131  { \
132    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
133  }
134
135#define _CPU_ISR_Enable( _isr_cookie )  \
136  { \
137    (void) (_isr_cookie);   /* prevent warnings from -Wunused-but-set-variable */ \
138  }
139
140#define _CPU_ISR_Flash( _isr_cookie ) \
141  { \
142  }
143
144RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
145{
146  return false;
147}
148
149#define _CPU_ISR_Set_level( new_level ) \
150  { \
151  }
152
153uint32_t   _CPU_ISR_Get_level( void );
154
155/* end of ISR handler macros */
156
157/* Context handler macros */
158#define _CPU_Context_Destroy( _the_thread, _the_context ) \
159  { \
160  }
161
162void _CPU_Context_Initialize(
163  Context_Control *the_context,
164  void *stack_area_begin,
165  size_t stack_area_size,
166  uint32_t new_level,
167  void (*entry_point)( void ),
168  bool is_fp,
169  void *tls_area
170);
171
172#define _CPU_Context_Restart_self( _the_context ) \
173   _CPU_Context_restore( (_the_context) );
174
175#define _CPU_Context_Initialize_fp( _destination )  \
176  { \
177   *(*(_destination)) = _CPU_Null_fp_context; \
178  }
179
180/* end of Context handler macros */
181
182/* Fatal Error manager macros */
183
184#define _CPU_Fatal_halt( _source, _error ) \
185  { \
186  }
187
188/* end of Fatal Error manager macros */
189
190/* Bitfield handler macros */
191
192#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
193
194#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
195#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
196  { \
197    (_output) = 0;   /* do something to prevent warnings */ \
198  }
199#endif
200
201/* end of Bitfield handler macros */
202
203#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
204#define _CPU_Priority_Mask( _bit_number ) \
205  ( 1 << (_bit_number) )
206#endif
207
208#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
209#define _CPU_Priority_bits_index( _priority ) \
210  (_priority)
211#endif
212
213/* end of Priority handler macros */
214
215/* functions */
216
217void _CPU_Initialize(void);
218
219void _CPU_ISR_install_raw_handler(
220  uint32_t    vector,
221  proc_ptr    new_handler,
222  proc_ptr   *old_handler
223);
224
225void _CPU_ISR_install_vector(
226  uint32_t    vector,
227  proc_ptr    new_handler,
228  proc_ptr   *old_handler
229);
230
231void _CPU_Install_interrupt_stack( void );
232
233void *_CPU_Thread_Idle_body( uintptr_t ignored );
234
235void _CPU_Context_switch(
236  Context_Control  *run,
237  Context_Control  *heir
238);
239
240void _CPU_Context_restore(
241  Context_Control *new_context
242) RTEMS_NO_RETURN;
243
244void _CPU_Context_save_fp(
245  Context_Control_fp **fp_context_ptr
246);
247
248void _CPU_Context_restore_fp(
249  Context_Control_fp **fp_context_ptr
250);
251
252typedef struct {
253  uint32_t processor_state_register;
254  uint32_t integer_registers [1];
255  double float_registers [1];
256} CPU_Exception_frame;
257
258void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
259
260static inline uint32_t CPU_swap_u32(
261  uint32_t value
262)
263{
264  uint32_t byte1, byte2, byte3, byte4, swapped;
265
266  byte4 = (value >> 24) & 0xff;
267  byte3 = (value >> 16) & 0xff;
268  byte2 = (value >> 8)  & 0xff;
269  byte1 =  value        & 0xff;
270
271  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
272  return swapped;
273}
274
275#define CPU_swap_u16( value ) \
276  (((value&0xff) << 8) | ((value >> 8)&0xff))
277
278typedef uint32_t CPU_Counter_ticks;
279
280uint32_t _CPU_Counter_frequency( void );
281
282CPU_Counter_ticks _CPU_Counter_read( void );
283
284
285static inline CPU_Counter_ticks _CPU_Counter_difference(
286  CPU_Counter_ticks second,
287  CPU_Counter_ticks first
288)
289{
290  return second - first;
291}
292
293#ifdef RTEMS_SMP
294   *
295  uint32_t _CPU_SMP_Initialize( void );
296
297  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
298
299  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
300
301  void _CPU_SMP_Prepare_start_multitasking( void );
302
303  static inline uint32_t _CPU_SMP_Get_current_processor( void )
304  {
305    return 123;
306  }
307
308  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
309
310  static inline void _CPU_SMP_Processor_event_broadcast( void )
311  {
312    __asm__ volatile ( "" : : : "memory" );
313  }
314
315  static inline void _CPU_SMP_Processor_event_receive( void )
316  {
317    __asm__ volatile ( "" : : : "memory" );
318  }
319
320  static inline bool _CPU_Context_Get_is_executing(
321    const Context_Control *context
322  )
323    return context->is_executing;
324  }
325
326  static inline void _CPU_Context_Set_is_executing(
327    Context_Control *context,
328    bool is_executing
329  )
330  {
331  }
332
333#endif /* RTEMS_SMP */
334
335typedef uintptr_t CPU_Uint32ptr;
336
337#ifdef __cplusplus
338}
339#endif
340
341#endif /* ASM */
342
343#endif /* _RTEMS_SCORE_CPU_H */
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