source: rtems/cpukit/score/cpu/x86_64/include/rtems/score/cpu.h @ 27bbc05

Last change on this file since 27bbc05 was 27bbc05, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 2, 2018 at 12:49:01 PM

score: Remove CPU_PARTITION_ALIGNMENT

Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.

It seems that previously the condition

CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)

was true on all CPU ports. Now, we need an additional check.

Update #3482.

  • Property mode set to 100644
File size: 7.9 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 *
4 * @brief x86_64 Dependent Source
5 *
6 * This include file contains information pertaining to the x86_64 processor.
7 */
8
9/*
10 * Copyright (c) 2018.
11 * Amaan Cheval <amaan.cheval@gmail.com>
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 *    notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 *    notice, this list of conditions and the following disclaimer in the
20 *    documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#ifndef _RTEMS_SCORE_CPU_H
36#define _RTEMS_SCORE_CPU_H
37
38#ifdef __cplusplus
39extern "C" {
40#endif
41
42#include <rtems/score/basedefs.h>
43#include <rtems/score/x86_64.h>
44
45#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
46#define CPU_ISR_PASSES_FRAME_POINTER FALSE
47// XXX: Enable FPU support
48#define CPU_HARDWARE_FP     FALSE
49#define CPU_SOFTWARE_FP     FALSE
50#define CPU_ALL_TASKS_ARE_FP     FALSE
51#define CPU_IDLE_TASK_IS_FP      FALSE
52#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
53#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
54#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
55#define CPU_STACK_GROWS_UP               FALSE
56
57#define CPU_STRUCTURE_ALIGNMENT __attribute__((aligned ( 64 )))
58#define CPU_CACHE_LINE_BYTES 64
59#define CPU_MODES_INTERRUPT_MASK   0x00000001
60#define CPU_MAXIMUM_PROCESSORS 32
61
62#define CPU_EFLAGS_INTERRUPTS_ON  0x00003202
63#define CPU_EFLAGS_INTERRUPTS_OFF 0x00003002
64
65#ifndef ASM
66
67typedef struct {
68  uint64_t rflags;
69
70  /**
71   * Callee-saved registers as listed in the SysV ABI document:
72   * https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI
73   */
74  uint64_t rbx;
75  void    *rsp;
76  void    *rbp;
77  uint64_t r12;
78  uint64_t r13;
79  uint64_t r14;
80  uint64_t r15;
81
82  // XXX: FS segment descriptor for TLS
83
84#ifdef RTEMS_SMP
85    volatile bool is_executing;
86#endif
87} Context_Control;
88
89#define _CPU_Context_Get_SP( _context ) \
90  (_context)->rsp
91
92typedef struct {
93  /* XXX: MMX, XMM, others?
94   *
95   * All x87 registers are caller-saved, so callees that make use of the MMX
96   * registers may use the faster femms instruction
97   */
98
99  /** FPU registers are listed here */
100  double      some_float_register;
101} Context_Control_fp;
102
103typedef struct {
104    uint32_t   special_interrupt_register;
105} CPU_Interrupt_frame;
106
107#endif /* ASM */
108
109
110#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
111#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
112#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
113#define CPU_STACK_MINIMUM_SIZE          (1024*4)
114#define CPU_SIZEOF_POINTER         8
115#define CPU_ALIGNMENT              8
116#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
117#define CPU_STACK_ALIGNMENT        16
118#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
119
120/*
121 *  ISR handler macros
122 */
123
124#ifndef ASM
125
126#define _CPU_Initialize_vectors()
127
128// XXX: For RTEMS critical sections
129#define _CPU_ISR_Disable( _isr_cookie ) \
130  { \
131    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
132  }
133
134#define _CPU_ISR_Enable( _isr_cookie )  \
135  { \
136    (void) (_isr_cookie);   /* prevent warnings from -Wunused-but-set-variable */ \
137  }
138
139#define _CPU_ISR_Flash( _isr_cookie ) \
140  { \
141  }
142
143RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
144{
145  return false;
146}
147
148#define _CPU_ISR_Set_level( new_level ) \
149  { \
150  }
151
152uint32_t   _CPU_ISR_Get_level( void );
153
154/* end of ISR handler macros */
155
156/* Context handler macros */
157#define _CPU_Context_Destroy( _the_thread, _the_context ) \
158  { \
159  }
160
161void _CPU_Context_Initialize(
162  Context_Control *the_context,
163  void *stack_area_begin,
164  size_t stack_area_size,
165  uint32_t new_level,
166  void (*entry_point)( void ),
167  bool is_fp,
168  void *tls_area
169);
170
171#define _CPU_Context_Restart_self( _the_context ) \
172   _CPU_Context_restore( (_the_context) );
173
174#define _CPU_Context_Initialize_fp( _destination )  \
175  { \
176   *(*(_destination)) = _CPU_Null_fp_context; \
177  }
178
179/* end of Context handler macros */
180
181/* Fatal Error manager macros */
182
183#define _CPU_Fatal_halt( _source, _error ) \
184  { \
185  }
186
187/* end of Fatal Error manager macros */
188
189/* Bitfield handler macros */
190
191#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
192
193#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
194#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
195  { \
196    (_output) = 0;   /* do something to prevent warnings */ \
197  }
198#endif
199
200/* end of Bitfield handler macros */
201
202#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
203#define _CPU_Priority_Mask( _bit_number ) \
204  ( 1 << (_bit_number) )
205#endif
206
207#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
208#define _CPU_Priority_bits_index( _priority ) \
209  (_priority)
210#endif
211
212/* end of Priority handler macros */
213
214/* functions */
215
216void _CPU_Initialize(void);
217
218void _CPU_ISR_install_raw_handler(
219  uint32_t    vector,
220  proc_ptr    new_handler,
221  proc_ptr   *old_handler
222);
223
224void _CPU_ISR_install_vector(
225  uint32_t    vector,
226  proc_ptr    new_handler,
227  proc_ptr   *old_handler
228);
229
230void _CPU_Install_interrupt_stack( void );
231
232void *_CPU_Thread_Idle_body( uintptr_t ignored );
233
234void _CPU_Context_switch(
235  Context_Control  *run,
236  Context_Control  *heir
237);
238
239void _CPU_Context_restore(
240  Context_Control *new_context
241) RTEMS_NO_RETURN;
242
243void _CPU_Context_save_fp(
244  Context_Control_fp **fp_context_ptr
245);
246
247void _CPU_Context_restore_fp(
248  Context_Control_fp **fp_context_ptr
249);
250
251typedef struct {
252  uint32_t processor_state_register;
253  uint32_t integer_registers [1];
254  double float_registers [1];
255} CPU_Exception_frame;
256
257void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
258
259static inline uint32_t CPU_swap_u32(
260  uint32_t value
261)
262{
263  uint32_t byte1, byte2, byte3, byte4, swapped;
264
265  byte4 = (value >> 24) & 0xff;
266  byte3 = (value >> 16) & 0xff;
267  byte2 = (value >> 8)  & 0xff;
268  byte1 =  value        & 0xff;
269
270  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
271  return swapped;
272}
273
274#define CPU_swap_u16( value ) \
275  (((value&0xff) << 8) | ((value >> 8)&0xff))
276
277typedef uint32_t CPU_Counter_ticks;
278
279uint32_t _CPU_Counter_frequency( void );
280
281CPU_Counter_ticks _CPU_Counter_read( void );
282
283
284static inline CPU_Counter_ticks _CPU_Counter_difference(
285  CPU_Counter_ticks second,
286  CPU_Counter_ticks first
287)
288{
289  return second - first;
290}
291
292#ifdef RTEMS_SMP
293   *
294  uint32_t _CPU_SMP_Initialize( void );
295
296  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
297
298  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
299
300  void _CPU_SMP_Prepare_start_multitasking( void );
301
302  static inline uint32_t _CPU_SMP_Get_current_processor( void )
303  {
304    return 123;
305  }
306
307  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
308
309  static inline void _CPU_SMP_Processor_event_broadcast( void )
310  {
311    __asm__ volatile ( "" : : : "memory" );
312  }
313
314  static inline void _CPU_SMP_Processor_event_receive( void )
315  {
316    __asm__ volatile ( "" : : : "memory" );
317  }
318
319  static inline bool _CPU_Context_Get_is_executing(
320    const Context_Control *context
321  )
322    return context->is_executing;
323  }
324
325  static inline void _CPU_Context_Set_is_executing(
326    Context_Control *context,
327    bool is_executing
328  )
329  {
330  }
331
332#endif /* RTEMS_SMP */
333
334typedef uintptr_t CPU_Uint32ptr;
335
336#ifdef __cplusplus
337}
338#endif
339
340#endif /* ASM */
341
342#endif /* _RTEMS_SCORE_CPU_H */
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