1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief x86_64 Dependent Source |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2018. |
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9 | * Amaan Cheval <amaan.cheval@gmail.com> |
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10 | * |
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11 | * Copyright (c) 1989-1999. |
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12 | * On-Line Applications Research Corporation (OAR). |
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13 | * |
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14 | * Redistribution and use in source and binary forms, with or without |
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15 | * modification, are permitted provided that the following conditions |
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16 | * are met: |
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17 | * 1. Redistributions of source code must retain the above copyright |
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18 | * notice, this list of conditions and the following disclaimer. |
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19 | * 2. Redistributions in binary form must reproduce the above copyright |
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20 | * notice, this list of conditions and the following disclaimer in the |
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21 | * documentation and/or other materials provided with the distribution. |
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22 | * |
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23 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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25 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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26 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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27 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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28 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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29 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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30 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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31 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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32 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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33 | * SUCH DAMAGE. |
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34 | */ |
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35 | |
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36 | #ifdef HAVE_CONFIG_H |
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37 | #include "config.h" |
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38 | #endif |
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39 | |
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40 | #include <rtems/system.h> |
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41 | #include <rtems/score/idt.h> |
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42 | #include <rtems/score/isr.h> |
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43 | #include <rtems/score/wkspace.h> |
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44 | #include <rtems/score/tls.h> |
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45 | |
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46 | Context_Control_fp _CPU_Null_fp_context; |
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47 | |
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48 | void _CPU_Exception_frame_print(const CPU_Exception_frame *ctx) |
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49 | { |
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50 | } |
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51 | |
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52 | void _CPU_Initialize(void) |
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53 | { |
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54 | } |
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55 | |
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56 | void _CPU_ISR_install_raw_handler( |
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57 | uint32_t vector, |
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58 | proc_ptr new_handler, |
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59 | proc_ptr *old_handler |
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60 | ) |
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61 | { |
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62 | amd64_install_raw_interrupt( |
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63 | vector, |
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64 | (uintptr_t) new_handler, |
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65 | (uintptr_t*) old_handler |
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66 | ); |
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67 | } |
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68 | |
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69 | void _CPU_ISR_install_vector( |
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70 | uint32_t vector, |
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71 | proc_ptr new_handler, |
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72 | proc_ptr *old_handler |
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73 | ) |
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74 | { |
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75 | } |
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76 | |
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77 | void *_CPU_Thread_Idle_body(uintptr_t ignored) |
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78 | { |
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79 | for ( ; ; ) { } |
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80 | } |
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