source: rtems/cpukit/score/cpu/v850/rtems/score/v850.h @ 2d7ae960

4.115
Last change on this file since 2d7ae960 was 2d7ae960, checked in by Joel Sherrill <joel.sherrill@…>, on 06/11/12 at 18:37:29

v850 port: Initial addition with BSP for simulator in GDB

Port

+ v850 does not have appear to have any optimized bit scan instructions
+ v850 does have single instructions for wap u16 and u32
+ Code path optimization preferences set
+ Add BSP variants for each GCC CPU model flag and a README

  • v850e1 variant does not work (fails during BSP initialization)

BSP for GDB v850 Simulator

+ linkcmds matches defaults in GDB simulator with RTEMS mods
+ crt1.c added from v850 newlib port for main()
+ BSP exits cleanly
+ printk and console I/O work
+ uses clock tick from IDLE task
+ Tests not requiring real clock ISR work

Documentation

+ CPU Supplment chapter for v850 added

  • Property mode set to 100644
File size: 3.4 KB
Line 
1/*
2 *  This file sets up basic CPU dependency settings based on
3 *  compiler settings.  For example, it can determine if
4 *  floating point is available.  This particular implementation
5 *  is specified to the Renesas v850 port.
6 */
7
8/*
9 *  COPYRIGHT (c) 1989-2012.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 */
16
17#ifndef _RTEMS_SCORE_V850_H
18#define _RTEMS_SCORE_V850_H
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 *  This file contains the information required to build
26 *  RTEMS for a particular member of the NO CPU family.
27 *  It does this by setting variables to indicate which
28 *  implementation dependent features are present in a particular
29 *  member of the family.
30 *
31 *  This is a good place to list all the known CPU models
32 *  that this port supports and which RTEMS CPU model they correspond
33 *  to.
34 */
35
36#if defined(rtems_multilib)
37/*
38 *  Figure out all CPU Model Feature Flags based upon compiler
39 *  predefines.
40 */
41#define CPU_MODEL_NAME  "rtems_multilib"
42#define V850_HAS_FPU 0
43
44#elif defined(__v850e2v3__)
45#define CPU_MODEL_NAME  "v850e2v3"
46#define V850_HAS_FPU 1
47
48#elif defined(__v850e2__)
49#define CPU_MODEL_NAME  "v850e2"
50#define V850_HAS_FPU 0
51
52#elif defined(__v850es__)
53#define CPU_MODEL_NAME  "v850es"
54#define V850_HAS_FPU 0
55
56#elif defined(__v850e1__)
57#define CPU_MODEL_NAME  "v850e1"
58#define V850_HAS_FPU 0
59
60#elif defined(__v850e__)
61#define CPU_MODEL_NAME  "v850e"
62#define V850_HAS_FPU 0
63
64#else
65#define CPU_MODEL_NAME  "v850"
66#define V850_HAS_FPU     0
67
68#endif
69
70/*
71 *  Define the name of the CPU family.
72 */
73#define CPU_NAME "v850 CPU"
74
75/*
76 *  Method to set the Program Status Word (PSW)
77 */
78#define v850_set_psw( _psw ) \
79    __asm__ __volatile__( "ldsr %0, psw" : : "r" (_psw) )
80
81/*
82 *  Method to obtain the Program Status Word (PSW)
83 */
84#define v850_get_psw( _psw ) \
85    __asm__ __volatile__( "stsr psw, %0" : "=&r" (_psw) )
86
87/*
88 *  Masks and bits in the Program Status Word (PSW)
89 */
90#define V850_PSW_ZERO_MASK                       0x01
91#define V850_PSW_IS_ZERO                         0x01
92#define V850_PSW_IS_NOT                          0x00
93
94#define V850_PSW_SIGN_MASK                       0x02
95#define V850_PSW_SIGN_IS_NEGATIVE                0x02
96#define V850_PSW_SIGN_IS_ZERO_OR_POSITIVE        0x00
97
98#define V850_PSW_OVERFLOW_MASK                   0x02
99#define V850_PSW_OVERFLOW_OCCURRED               0x02
100#define V850_PSW_OVERFLOW_DID_NOT_OCCUR          0x00
101
102#define V850_PSW_CARRY_OR_BORROW_MASK            0x04
103#define V850_PSW_CARRY_OR_BORROW_OCCURRED        0x04
104#define V850_PSW_CARRY_OR_BORROW_DID_NOT_OCCUR   0x00
105
106#define V850_PSW_SATURATION_MASK                 0x10
107#define V850_PSW_SATURATION_OCCURRED             0x10
108#define V850_PSW_SATURATION_DID_NOT_OCCUR        0x00
109
110#define V850_PSW_INTERRUPT_DISABLE_MASK          0x20
111#define V850_PSW_INTERRUPT_DISABLE               0x20
112#define V850_PSW_INTERRUPT_ENABLE                0x00
113
114#define V850_PSW_EXCEPTION_IN_PROCESS_MASK       0x40
115#define V850_PSW_EXCEPTION_IN_PROCESS            0x40
116#define V850_PSW_EXCEPTION_NOT_IN_PROCESS        0x00
117
118#define V850_PSW_NMI_IN_PROCESS_MASK             0x80
119#define V850_PSW_NMI_IN_PROCESS                  0x80
120#define V850_PSW_NMI_NOT_IN_PROCESS              0x00
121
122#ifdef __cplusplus
123}
124#endif
125
126#endif /* _RTEMS_SCORE_V850_H */
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