source: rtems/cpukit/score/cpu/v850/rtems/score/cpu.h @ f570b071

4.11
Last change on this file since f570b071 was f570b071, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 1, 2014 at 8:20:01 AM

score: Rename Priority_bit_map_Control

Rename Priority_bit_map_Control in Priority_bit_map_Word.

  • Property mode set to 100644
File size: 39.5 KB
Line 
1/**
2 * @file
3 *
4 * @brief V850 CPU Department Source
5 *
6 * This include file contains information pertaining to the v850
7 * processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2012.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/v850.h>
28
29/* conditional compilation parameters */
30
31/**
32 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
33 *
34 * If TRUE, then they are inlined.
35 * If FALSE, then a subroutine call is made.
36 *
37 * This conditional is an example of the classic trade-off of size
38 * versus speed.  Inlining the call (TRUE) typically increases the
39 * size of RTEMS while speeding up the enabling of dispatching.
40 *
41 * @note In general, the @ref _Thread_Dispatch_disable_level will
42 * only be 0 or 1 unless you are in an interrupt handler and that
43 * interrupt handler invokes the executive.]  When not inlined
44 * something calls @ref _Thread_Enable_dispatch which in turns calls
45 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
46 * one subroutine call is avoided entirely.
47 *
48 * Port Specific Information:
49 *
50 * The v850 is a RISC CPU which typically has enough memory to justify
51 * the inlining of this method.
52 */
53#define CPU_INLINE_ENABLE_DISPATCH       TRUE
54
55/**
56 * Should the body of the search loops in _Thread_queue_Enqueue_priority
57 * be unrolled one time?  In unrolled each iteration of the loop examines
58 * two "nodes" on the chain being searched.  Otherwise, only one node
59 * is examined per iteration.
60 *
61 * If TRUE, then the loops are unrolled.
62 * If FALSE, then the loops are not unrolled.
63 *
64 * The primary factor in making this decision is the cost of disabling
65 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
66 * body of the loop.  On some CPUs, the flash is more expensive than
67 * one iteration of the loop body.  In this case, it might be desirable
68 * to unroll the loop.  It is important to note that on some CPUs, this
69 * code is the longest interrupt disable period in RTEMS.  So it is
70 * necessary to strike a balance when setting this parameter.
71 *
72 * Port Specific Information:
73 *
74 * The v850 is a RISC CPU which typically has enough memory to justify
75 * the unrolling of this method.
76 */
77#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
78
79/**
80 * Does RTEMS manage a dedicated interrupt stack in software?
81 *
82 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
83 * If FALSE, nothing is done.
84 *
85 * If the CPU supports a dedicated interrupt stack in hardware,
86 * then it is generally the responsibility of the BSP to allocate it
87 * and set it up.
88 *
89 * If the CPU does not support a dedicated interrupt stack, then
90 * the porter has two options: (1) execute interrupts on the
91 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
92 * interrupt stack.
93 *
94 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
95 *
96 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
97 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
98 * possible that both are FALSE for a particular CPU.  Although it
99 * is unclear what that would imply about the interrupt processing
100 * procedure on that CPU.
101 *
102 * Port Specific Information:
103 *
104 * The v850 does not have support for a hardware interrupt stack.
105 */
106#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
107
108/**
109 * Does the CPU follow the simple vectored interrupt model?
110 *
111 * If TRUE, then RTEMS allocates the vector table it internally manages.
112 * If FALSE, then the BSP is assumed to allocate and manage the vector
113 * table
114 *
115 * Port Specific Information:
116 *
117 * This port uses the Progammable Interrupt Controller interrupt model.
118 */
119#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
120
121/**
122 * Does this CPU have hardware support for a dedicated interrupt stack?
123 *
124 * If TRUE, then it must be installed during initialization.
125 * If FALSE, then no installation is performed.
126 *
127 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
128 *
129 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
130 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
131 * possible that both are FALSE for a particular CPU.  Although it
132 * is unclear what that would imply about the interrupt processing
133 * procedure on that CPU.
134 *
135 * Port Specific Information:
136 *
137 * The v850 does not have support for a hardware interrupt stack.
138 */
139#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
140
141/**
142 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
143 *
144 * If TRUE, then the memory is allocated during initialization.
145 * If FALSE, then the memory is allocated during initialization.
146 *
147 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
148 *
149 * Port Specific Information:
150 *
151 * XXX document implementation including references if appropriate
152 */
153#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
154
155/**
156 * @def CPU_HARDWARE_FP
157 *
158 * Does the CPU have hardware floating point?
159 *
160 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
161 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
162 *
163 * If there is a FP coprocessor such as the i387 or mc68881, then
164 * the answer is TRUE.
165 *
166 * The macro name "V850_HAS_FPU" should be made CPU specific.
167 * It indicates whether or not this CPU model has FP support.  For
168 * example, it would be possible to have an i386_nofp CPU model
169 * which set this to false to indicate that you have an i386 without
170 * an i387 and wish to leave floating point support out of RTEMS.
171 */
172
173/**
174 * @def CPU_SOFTWARE_FP
175 *
176 * Does the CPU have no hardware floating point and GCC provides a
177 * software floating point implementation which must be context
178 * switched?
179 *
180 * This feature conditional is used to indicate whether or not there
181 * is software implemented floating point that must be context
182 * switched.  The determination of whether or not this applies
183 * is very tool specific and the state saved/restored is also
184 * compiler specific.
185 *
186 * Port Specific Information:
187 *
188 * Some v850 models do have IEEE hardware floating point support but
189 * they do not have any special registers to save or bit(s) which
190 * determine if the FPU is enabled. In short, there appears to be nothing
191 * related to the floating point operations which impact the RTEMS
192 * thread context switch. Thus from an RTEMS perspective, there is really
193 * no FPU to manage.
194 */
195#define CPU_HARDWARE_FP     FALSE
196#define CPU_SOFTWARE_FP     FALSE
197
198/**
199 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
200 *
201 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
202 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
203 *
204 * So far, the only CPUs in which this option has been used are the
205 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
206 * gcc both implicitly used the floating point registers to perform
207 * integer multiplies.  Similarly, the PowerPC port of gcc has been
208 * seen to allocate floating point local variables and touch the FPU
209 * even when the flow through a subroutine (like vfprintf()) might
210 * not use floating point formats.
211 *
212 * If a function which you would not think utilize the FP unit DOES,
213 * then one can not easily predict which tasks will use the FP hardware.
214 * In this case, this option should be TRUE.
215 *
216 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
217 *
218 * Port Specific Information:
219 *
220 * This should be false until it has been demonstrated that gcc for the
221 * v850 generates FPU code when it is unexpected. But even this would
222 * not matter since there are no FP specific registers or bits which
223 * would be corrupted if an FP operation occurred in an integer only
224 * thread.
225 */
226#define CPU_ALL_TASKS_ARE_FP     FALSE
227
228/**
229 * Should the IDLE task have a floating point context?
230 *
231 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
232 * and it has a floating point context which is switched in and out.
233 * If FALSE, then the IDLE task does not have a floating point context.
234 *
235 * Setting this to TRUE negatively impacts the time required to preempt
236 * the IDLE task from an interrupt because the floating point context
237 * must be saved as part of the preemption.
238 *
239 * Port Specific Information:
240 *
241 * The IDLE thread should not be using the FPU. Leave this off.
242 */
243#define CPU_IDLE_TASK_IS_FP      FALSE
244
245/**
246 * Should the saving of the floating point registers be deferred
247 * until a context switch is made to another different floating point
248 * task?
249 *
250 * If TRUE, then the floating point context will not be stored until
251 * necessary.  It will remain in the floating point registers and not
252 * disturned until another floating point task is switched to.
253 *
254 * If FALSE, then the floating point context is saved when a floating
255 * point task is switched out and restored when the next floating point
256 * task is restored.  The state of the floating point registers between
257 * those two operations is not specified.
258 *
259 * If the floating point context does NOT have to be saved as part of
260 * interrupt dispatching, then it should be safe to set this to TRUE.
261 *
262 * Setting this flag to TRUE results in using a different algorithm
263 * for deciding when to save and restore the floating point context.
264 * The deferred FP switch algorithm minimizes the number of times
265 * the FP context is saved and restored.  The FP context is not saved
266 * until a context switch is made to another, different FP task.
267 * Thus in a system with only one FP task, the FP context will never
268 * be saved or restored.
269 *
270 * Port Specific Information:
271 *
272 * See earlier comments. There is no FPU state to manage.
273 */
274#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
275
276/**
277 * Does this port provide a CPU dependent IDLE task implementation?
278 *
279 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
280 * must be provided and is the default IDLE thread body instead of
281 * @ref _CPU_Thread_Idle_body.
282 *
283 * If FALSE, then use the generic IDLE thread body if the BSP does
284 * not provide one.
285 *
286 * This is intended to allow for supporting processors which have
287 * a low power or idle mode.  When the IDLE thread is executed, then
288 * the CPU can be powered down.
289 *
290 * The order of precedence for selecting the IDLE thread body is:
291 *
292 *   -#  BSP provided
293 *   -#  CPU dependent (if provided)
294 *   -#  generic (if no BSP and no CPU dependent)
295 *
296 * Port Specific Information:
297 *
298 * There does not appear to be a reason for the v850 port itself to provide
299 * a special idle task.
300 */
301#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
302
303/**
304 * Does the stack grow up (toward higher addresses) or down
305 * (toward lower addresses)?
306 *
307 * If TRUE, then the grows upward.
308 * If FALSE, then the grows toward smaller addresses.
309 *
310 * Port Specific Information:
311 *
312 * The v850 stack grows from high addresses to low addresses.
313 */
314#define CPU_STACK_GROWS_UP               FALSE
315
316/**
317 * The following is the variable attribute used to force alignment
318 * of critical RTEMS structures.  On some processors it may make
319 * sense to have these aligned on tighter boundaries than
320 * the minimum requirements of the compiler in order to have as
321 * much of the critical data area as possible in a cache line.
322 *
323 * The placement of this macro in the declaration of the variables
324 * is based on the syntactically requirements of the GNU C
325 * "__attribute__" extension.  For example with GNU C, use
326 * the following to force a structures to a 32 byte boundary.
327 *
328 *     __attribute__ ((aligned (32)))
329 *
330 * @note Currently only the Priority Bit Map table uses this feature.
331 *       To benefit from using this, the data must be heavily
332 *       used so it will stay in the cache and used frequently enough
333 *       in the executive to justify turning this on.
334 *
335 * Port Specific Information:
336 *
337 * Until proven otherwise, use the compiler default.
338 */
339#define CPU_STRUCTURE_ALIGNMENT
340
341/**
342 * The v850 should use 64-bit timestamps and inline them.
343 */
344#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
345
346/**
347 * @defgroup CPUEndian Processor Dependent Endianness Support
348 *
349 * This group assists in issues related to processor endianness.
350 *
351 */
352/**@{**/
353
354/**
355 * Define what is required to specify how the network to host conversion
356 * routines are handled.
357 *
358 * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
359 * same values.
360 *
361 * @see CPU_LITTLE_ENDIAN
362 *
363 * Port Specific Information:
364 *
365 * The v850 is little endian.
366 */
367#define CPU_BIG_ENDIAN  FALSE
368
369/**
370 * Define what is required to specify how the network to host conversion
371 * routines are handled.
372 *
373 * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
374 * same values.
375 *
376 * @see CPU_BIG_ENDIAN
377 *
378 * Port Specific Information:
379 *
380 * The v850 is little endian.
381 */
382#define CPU_LITTLE_ENDIAN TRUE
383
384/** @} */
385
386/**
387 * @ingroup CPUInterrupt
388 * The following defines the number of bits actually used in the
389 * interrupt field of the task mode.  How those bits map to the
390 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
391 *
392 * Port Specific Information:
393 *
394 * The v850 only has a single bit in the CPU for interrupt disable/enable.
395 */
396#define CPU_MODES_INTERRUPT_MASK   0x00000001
397
398#define CPU_PER_CPU_CONTROL_SIZE 0
399
400typedef struct {
401  /* There is no CPU specific per-CPU state */
402} CPU_Per_CPU_control;
403
404/**
405 * @defgroup CPUContext Processor Dependent Context Management
406 *
407 * From the highest level viewpoint, there are 2 types of context to save.
408 *
409 *    -# Interrupt registers to save
410 *    -# Task level registers to save
411 *
412 * Since RTEMS handles integer and floating point contexts separately, this
413 * means we have the following 3 context items:
414 *
415 *    -# task level context stuff::  Context_Control
416 *    -# floating point task stuff:: Context_Control_fp
417 *    -# special interrupt level context :: CPU_Interrupt_frame
418 *
419 * On some processors, it is cost-effective to save only the callee
420 * preserved registers during a task context switch.  This means
421 * that the ISR code needs to save those registers which do not
422 * persist across function calls.  It is not mandatory to make this
423 * distinctions between the caller/callee saves registers for the
424 * purpose of minimizing context saved during task switch and on interrupts.
425 * If the cost of saving extra registers is minimal, simplicity is the
426 * choice.  Save the same context on interrupt entry as for tasks in
427 * this case.
428 *
429 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
430 * care should be used in designing the context area.
431 *
432 * On some CPUs with hardware floating point support, the Context_Control_fp
433 * structure will not be used or it simply consist of an array of a
434 * fixed number of bytes.   This is done when the floating point context
435 * is dumped by a "FP save context" type instruction and the format
436 * is not really defined by the CPU.  In this case, there is no need
437 * to figure out the exact format -- only the size.  Of course, although
438 * this is enough information for RTEMS, it is probably not enough for
439 * a debugger such as gdb.  But that is another problem.
440 *
441 * Port Specific Information:
442 *
443 * On the v850, this port saves special registers and those that are
444 * callee saved.
445 */
446/**@{**/
447
448/**
449 * This defines the minimal set of integer and processor state registers
450 * that must be saved during a voluntary context switch from one thread
451 * to another.
452 */
453typedef struct {
454    uint32_t   r1;
455    /** This field is the stack pointer (e.g. r3).  */
456    uint32_t   r3_stack_pointer;
457    uint32_t   r20;
458    uint32_t   r21;
459    uint32_t   r22;
460    uint32_t   r23;
461    uint32_t   r24;
462    uint32_t   r25;
463    uint32_t   r26;
464    uint32_t   r27;
465    uint32_t   r28;
466    uint32_t   r29;
467    uint32_t   r31;
468    uint32_t   psw;
469} Context_Control;
470
471/**
472 * This macro returns the stack pointer associated with @a _context.
473 *
474 * @param[in] _context is the thread context area to access
475 *
476 * @return This method returns the stack pointer.
477 */
478#define _CPU_Context_Get_SP( _context ) \
479  (_context)->r3_stack_pointer
480
481/**
482 * This defines the complete set of floating point registers that must
483 * be saved during any context switch from one thread to another.
484 */
485typedef struct {
486    /** FPU registers are listed here */
487    double      some_float_register;
488} Context_Control_fp;
489
490/**
491 * This defines the set of integer and processor state registers that must
492 * be saved during an interrupt.  This set does not include any which are
493 * in @ref Context_Control.
494 */
495typedef struct {
496    /** This field is a hint that a port will have a number of integer
497     * registers that need to be saved when an interrupt occurs or
498     * when a context switch occurs at the end of an ISR.
499     */
500    uint32_t   special_interrupt_register;
501} CPU_Interrupt_frame;
502
503/** @} */
504
505/**
506 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
507 *
508 * On some CPUs, RTEMS supports a software managed interrupt stack.
509 * This stack is allocated by the Interrupt Manager and the switch
510 * is performed in @ref _ISR_Handler.  These variables contain pointers
511 * to the lowest and highest addresses in the chunk of memory allocated
512 * for the interrupt stack.  Since it is unknown whether the stack
513 * grows up or down (in general), this give the CPU dependent
514 * code the option of picking the version it wants to use.
515 *
516 * @note These two variables are required if the macro
517 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
518 *
519 * Port Specific Information:
520 *
521 * XXX document implementation including references if appropriate
522 */
523/**@{**/
524
525/**
526 * @ingroup CPUContext
527 * The size of the floating point context area.  On some CPUs this
528 * will not be a "sizeof" because the format of the floating point
529 * area is not defined -- only the size is.  This is usually on
530 * CPUs with a "floating point save context" instruction.
531 *
532 * Port Specific Information:
533 *
534 * The v850 does not need a floating point context but this needs to be
535 * defined so confdefs.h.
536 */
537/* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */
538#define CPU_CONTEXT_FP_SIZE 0
539
540/**
541 * Amount of extra stack (above minimum stack size) required by
542 * MPCI receive server thread.  Remember that in a multiprocessor
543 * system this thread must exist and be able to process all directives.
544 *
545 * Port Specific Information:
546 *
547 * There is no reason to think the v850 needs extra MPCI receive
548 * server stack.
549 */
550#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
551
552/* XXX this should not be needed on PIC architectures */
553/* XXX evaluate removing it */
554#if 0
555/**
556 * This defines the number of entries in the @ref _ISR_Vector_table managed
557 * by RTEMS.
558 *
559 * Port Specific Information:
560 *
561 * XXX document implementation including references if appropriate
562 */
563#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
564#endif
565
566/**
567 * This defines the highest interrupt vector number for this port.
568 */
569#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
570
571/**
572 * This is defined if the port has a special way to report the ISR nesting
573 * level.  Most ports maintain the variable @a _ISR_Nest_level.
574 */
575#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
576
577/** @} */
578
579/**
580 * @ingroup CPUContext
581 * Should be large enough to run all RTEMS tests.  This ensures
582 * that a "reasonable" small application should not have any problems.
583 *
584 * Port Specific Information:
585 *
586 * This should be very conservative on the v850.
587 */
588#define CPU_STACK_MINIMUM_SIZE          (1024*4)
589
590#define CPU_SIZEOF_POINTER 4
591
592/**
593 * CPU's worst alignment requirement for data types on a byte boundary.  This
594 * alignment does not take into account the requirements for the stack.
595 *
596 * Port Specific Information:
597 *
598 * There is no apparent reason why this should be larger than 8.
599 */
600#define CPU_ALIGNMENT              8
601
602/**
603 * This number corresponds to the byte alignment requirement for the
604 * heap handler.  This alignment requirement may be stricter than that
605 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
606 * common for the heap to follow the same alignment requirement as
607 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
608 * the heap, then this should be set to @ref CPU_ALIGNMENT.
609 *
610 * @note  This does not have to be a power of 2 although it should be
611 *        a multiple of 2 greater than or equal to 2.  The requirement
612 *        to be a multiple of 2 is because the heap uses the least
613 *        significant field of the front and back flags to indicate
614 *        that a block is in use or free.  So you do not want any odd
615 *        length blocks really putting length data in that bit.
616 *
617 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
618 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
619 *        elements allocated from the heap meet all restrictions.
620 *
621 * Port Specific Information:
622 *
623 * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
624 */
625#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
626
627/**
628 * This number corresponds to the byte alignment requirement for memory
629 * buffers allocated by the partition manager.  This alignment requirement
630 * may be stricter than that for the data types alignment specified by
631 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
632 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
633 * strict enough for the partition, then this should be set to
634 * @ref CPU_ALIGNMENT.
635 *
636 * @note  This does not have to be a power of 2.  It does have to
637 *        be greater or equal to than @ref CPU_ALIGNMENT.
638 *
639 * Port Specific Information:
640 *
641 * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
642 */
643#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
644
645/**
646 * This number corresponds to the byte alignment requirement for the
647 * stack.  This alignment requirement may be stricter than that for the
648 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
649 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
650 * set to 0.
651 *
652 * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
653 *
654 * Port Specific Information:
655 *
656 * The v850 has enough RAM where alignment to 16 may be desirable depending
657 * on the cache properties. But this remains to be demonstrated.
658 */
659#define CPU_STACK_ALIGNMENT        4
660
661/*
662 *  ISR handler macros
663 */
664
665/**
666 * @addtogroup CPUInterrupt
667 */
668/**@{**/
669
670/**
671 * Disable all interrupts for an RTEMS critical section.  The previous
672 * level is returned in @a _isr_cookie.
673 *
674 * @param[out] _isr_cookie will contain the previous level cookie
675 *
676 * Port Specific Information:
677 *
678 * On the v850, we need to save the PSW and use "di" to disable interrupts.
679 */
680#define _CPU_ISR_Disable( _isr_cookie ) \
681  do { \
682    unsigned int _psw; \
683    \
684    v850_get_psw( _psw ); \
685    __asm__ __volatile__( "di" ); \
686    _isr_cookie = _psw; \
687  } while (0)
688
689/**
690 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
691 * This indicates the end of an RTEMS critical section.  The parameter
692 * @a _isr_cookie is not modified.
693 *
694 * @param[in] _isr_cookie contain the previous level cookie
695 *
696 * Port Specific Information:
697 *
698 * On the v850, we simply need to restore the PSW.
699 */
700#define _CPU_ISR_Enable( _isr_cookie )  \
701  do { \
702    unsigned int _psw = (_isr_cookie); \
703    \
704    v850_set_psw( _psw ); \
705  } while (0)
706
707/**
708 * This temporarily restores the interrupt to @a _isr_cookie before immediately
709 * disabling them again.  This is used to divide long RTEMS critical
710 * sections into two or more parts.  The parameter @a _isr_cookie is not
711 * modified.
712 *
713 * @param[in] _isr_cookie contain the previous level cookie
714 *
715 * Port Specific Information:
716 *
717 * This saves at least one instruction over using enable/disable back to back.
718 */
719#define _CPU_ISR_Flash( _isr_cookie ) \
720  do { \
721    unsigned int _psw = (_isr_cookie); \
722    v850_set_psw( _psw ); \
723    __asm__ __volatile__( "di" ); \
724  } while (0)
725
726/**
727 * This routine and @ref _CPU_ISR_Get_level
728 * Map the interrupt level in task mode onto the hardware that the CPU
729 * actually provides.  Currently, interrupt levels which do not
730 * map onto the CPU in a generic fashion are undefined.  Someday,
731 * it would be nice if these were "mapped" by the application
732 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
733 * 8 - 255 would be available for bsp/application specific meaning.
734 * This could be used to manage a programmable interrupt controller
735 * via the rtems_task_mode directive.
736 *
737 * Port Specific Information:
738 *
739 * On the v850, level 0 is enabled. Non-zero is disabled.
740 */
741#define _CPU_ISR_Set_level( new_level ) \
742  do { \
743    if ( new_level ) \
744      __asm__ __volatile__( "di" ); \
745    else \
746      __asm__ __volatile__( "ei" ); \
747  } while (0)
748
749/**
750 * Return the current interrupt disable level for this task in
751 * the format used by the interrupt level portion of the task mode.
752 *
753 * @note This routine usually must be implemented as a subroutine.
754 *
755 * Port Specific Information:
756 *
757 * This method is implemented in C on the v850.
758 */
759uint32_t   _CPU_ISR_Get_level( void );
760
761/* end of ISR handler macros */
762
763/** @} */
764
765/* Context handler macros */
766
767/**
768 * @ingroup CPUContext
769 * Initialize the context to a state suitable for starting a
770 * task after a context restore operation.  Generally, this
771 * involves:
772 *
773 *    - setting a starting address
774 *    - preparing the stack
775 *    - preparing the stack and frame pointers
776 *    - setting the proper interrupt level in the context
777 *    - initializing the floating point context
778 *
779 * This routine generally does not set any unnecessary register
780 * in the context.  The state of the "general data" registers is
781 * undefined at task start time.
782 *
783 * @param[in] _the_context is the context structure to be initialized
784 * @param[in] _stack_base is the lowest physical address of this task's stack
785 * @param[in] _size is the size of this task's stack
786 * @param[in] _isr is the interrupt disable level
787 * @param[in] _entry_point is the thread's entry point.  This is
788 *        always @a _Thread_Handler
789 * @param[in] _is_fp is TRUE if the thread is to be a floating
790 *       point thread.  This is typically only used on CPUs where the
791 *       FPU may be easily disabled by software such as on the SPARC
792 *       where the PSR contains an enable FPU bit.
793 * @param[in] tls_area is the thread-local storage (TLS) area
794 *
795 * Port Specific Information:
796 *
797 * This method is implemented in C on the v850.
798 */
799void _CPU_Context_Initialize(
800  Context_Control  *the_context,
801  uint32_t         *stack_base,
802  uint32_t          size,
803  uint32_t          new_level,
804  void             *entry_point,
805  bool              is_fp,
806  void             *tls_area
807);
808
809/**
810 * This routine is responsible for somehow restarting the currently
811 * executing task.  If you are lucky, then all that is necessary
812 * is restoring the context.  Otherwise, there will need to be
813 * a special assembly routine which does something special in this
814 * case.  For many ports, simply adding a label to the restore path
815 * of @ref _CPU_Context_switch will work.  On other ports, it may be
816 * possibly to load a few arguments and jump to the restore path. It will
817 * not work if restarting self conflicts with the stack frame
818 * assumptions of restoring a context.
819 *
820 * Port Specific Information:
821 *
822 * On the v850, we require a special entry point to restart a task.
823 */
824#define _CPU_Context_Restart_self( _the_context ) \
825   _CPU_Context_restore( (_the_context) );
826
827/* XXX this should be possible to remove */
828#if 0
829/**
830 * @ingroup CPUContext
831 * The purpose of this macro is to allow the initial pointer into
832 * a floating point context area (used to save the floating point
833 * context) to be at an arbitrary place in the floating point
834 * context area.
835 *
836 * This is necessary because some FP units are designed to have
837 * their context saved as a stack which grows into lower addresses.
838 * Other FP units can be saved by simply moving registers into offsets
839 * from the base of the context area.  Finally some FP units provide
840 * a "dump context" instruction which could fill in from high to low
841 * or low to high based on the whim of the CPU designers.
842 *
843 * @param[in] _base is the lowest physical address of the floating point
844 *        context area
845 * @param[in] _offset is the offset into the floating point area
846 *
847 * Port Specific Information:
848 *
849 * XXX document implementation including references if appropriate
850 */
851#define _CPU_Context_Fp_start( _base, _offset ) \
852   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
853#endif
854
855/* XXX this should be possible to remove */
856#if 0
857/**
858 * This routine initializes the FP context area passed to it to.
859 * There are a few standard ways in which to initialize the
860 * floating point context.  The code included for this macro assumes
861 * that this is a CPU in which a "initial" FP context was saved into
862 * @a _CPU_Null_fp_context and it simply copies it to the destination
863 * context passed to it.
864 *
865 * Other floating point context save/restore models include:
866 *   -# not doing anything, and
867 *   -# putting a "null FP status word" in the correct place in the FP context.
868 *
869 * @param[in] _destination is the floating point context area
870 *
871 * Port Specific Information:
872 *
873 * XXX document implementation including references if appropriate
874 */
875#define _CPU_Context_Initialize_fp( _destination ) \
876  { \
877  }
878#endif
879
880/* end of Context handler macros */
881
882/* Fatal Error manager macros */
883
884/**
885 * This routine copies _error into a known place -- typically a stack
886 * location or a register, optionally disables interrupts, and
887 * halts/stops the CPU.
888 *
889 * Port Specific Information:
890 *
891 * Move the error code into r10, disable interrupts and halt.
892 */
893#define _CPU_Fatal_halt( _error ) \
894  do { \
895    __asm__ __volatile__ ( "di" ); \
896    __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \
897    __asm__ __volatile__ ( "halt" ); \
898  } while (0)
899
900/* end of Fatal Error manager macros */
901
902/* Bitfield handler macros */
903
904/**
905 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
906 *
907 * This set of routines are used to implement fast searches for
908 * the most important ready task.
909 */
910/**@{**/
911
912/**
913 * This definition is set to TRUE if the port uses the generic bitfield
914 * manipulation implementation.
915 */
916#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
917
918/**
919 * This definition is set to TRUE if the port uses the data tables provided
920 * by the generic bitfield manipulation implementation.
921 * This can occur when actually using the generic bitfield manipulation
922 * implementation or when implementing the same algorithm in assembly
923 * language for improved performance.  It is unlikely that a port will use
924 * the data if it has a bitfield scan instruction.
925 *
926 * Port Specific Information:
927 *
928 * There is no single v850 instruction to do a bit scan so there is
929 * no CPU specific implementation of bit field scanning. The empty
930 * stub routines are left as a place holder in case someone figures
931 * out how to do a v850 implementation better than the generic algorithm.
932 */
933#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
934
935/**
936 * This routine sets @a _output to the bit number of the first bit
937 * set in @a _value.  @a _value is of CPU dependent type
938 * @a Priority_bit_map_Word.  This type may be either 16 or 32 bits
939 * wide although only the 16 least significant bits will be used.
940 *
941 * There are a number of variables in using a "find first bit" type
942 * instruction.
943 *
944 *   -# What happens when run on a value of zero?
945 *   -# Bits may be numbered from MSB to LSB or vice-versa.
946 *   -# The numbering may be zero or one based.
947 *   -# The "find first bit" instruction may search from MSB or LSB.
948 *
949 * RTEMS guarantees that (1) will never happen so it is not a concern.
950 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
951 * @ref _CPU_Priority_bits_index.  These three form a set of routines
952 * which must logically operate together.  Bits in the _value are
953 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
954 * The basic major and minor values calculated by @ref _Priority_Major
955 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
956 * to properly range between the values returned by the "find first bit"
957 * instruction.  This makes it possible for @ref _Priority_Get_highest to
958 * calculate the major and directly index into the minor table.
959 * This mapping is necessary to ensure that 0 (a high priority major/minor)
960 * is the first bit found.
961 *
962 * This entire "find first bit" and mapping process depends heavily
963 * on the manner in which a priority is broken into a major and minor
964 * components with the major being the 4 MSB of a priority and minor
965 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
966 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
967 * to the lowest priority.
968 *
969 * If your CPU does not have a "find first bit" instruction, then
970 * there are ways to make do without it.  Here are a handful of ways
971 * to implement this in software:
972 *
973@verbatim
974      - a series of 16 bit test instructions
975      - a "binary search using if's"
976      - _number = 0
977        if _value > 0x00ff
978          _value >>=8
979          _number = 8;
980
981        if _value > 0x0000f
982          _value >=8
983          _number += 4
984
985        _number += bit_set_table[ _value ]
986@endverbatim
987
988 *   where bit_set_table[ 16 ] has values which indicate the first
989 *     bit set
990 *
991 * @param[in] _value is the value to be scanned
992 * @param[in] _output is the first bit set
993 *
994 * Port Specific Information:
995 *
996 * There is no single v850 instruction to do a bit scan so there is
997 * no CPU specific implementation of bit field scanning.
998 */
999#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1000#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1001  { \
1002    (_output) = 0;   /* do something to prevent warnings */ \
1003  }
1004#endif
1005
1006/* end of Bitfield handler macros */
1007
1008/**
1009 * This routine builds the mask which corresponds to the bit fields
1010 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1011 * for that routine.
1012 *
1013 * Port Specific Information:
1014 *
1015 * There is no single v850 instruction to do a bit scan so there is
1016 * no CPU specific implementation of bit field scanning.
1017 */
1018#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1019
1020#define _CPU_Priority_Mask( _bit_number ) \
1021  ( 1 << (_bit_number) )
1022
1023#endif
1024
1025/**
1026 * This routine translates the bit numbers returned by
1027 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1028 * a major or minor component of a priority.  See the discussion
1029 * for that routine.
1030 *
1031 * @param[in] _priority is the major or minor number to translate
1032 *
1033 * Port Specific Information:
1034 *
1035 * There is no single v850 instruction to do a bit scan so there is
1036 * no CPU specific implementation of bit field scanning.
1037 */
1038#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1039
1040#define _CPU_Priority_bits_index( _priority ) \
1041  (_priority)
1042
1043#endif
1044
1045/* end of Priority handler macros */
1046
1047/** @} */
1048
1049/* functions */
1050
1051/**
1052 * @brief CPU initialize.
1053 * This routine performs CPU dependent initialization.
1054 *
1055 * Port Specific Information:
1056 *
1057 * This is implemented in C.
1058 *
1059 * v850 CPU Dependent Source
1060 */
1061void _CPU_Initialize(void);
1062
1063/**
1064 * @addtogroup CPUContext
1065 */
1066/**@{**/
1067
1068/**
1069 * This routine switches from the run context to the heir context.
1070 *
1071 * @param[in] run points to the context of the currently executing task
1072 * @param[in] heir points to the context of the heir task
1073 *
1074 * Port Specific Information:
1075 *
1076 * This is implemented in assembly on the v850.
1077 */
1078void _CPU_Context_switch(
1079  Context_Control  *run,
1080  Context_Control  *heir
1081);
1082
1083/**
1084 * This routine is generally used only to restart self in an
1085 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1086 *
1087 * @param[in] new_context points to the context to be restored.
1088 *
1089 * @note May be unnecessary to reload some registers.
1090 *
1091 * Port Specific Information:
1092 *
1093 * This is implemented in assembly on the v850.
1094 */
1095void _CPU_Context_restore(
1096  Context_Control *new_context
1097) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1098
1099/* XXX this should be possible to remove */
1100#if 0
1101/**
1102 * This routine saves the floating point context passed to it.
1103 *
1104 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1105 * point context area
1106 *
1107 * @return on output @a *fp_context_ptr will contain the address that
1108 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1109 *
1110 * Port Specific Information:
1111 *
1112 * XXX document implementation including references if appropriate
1113 */
1114void _CPU_Context_save_fp(
1115  Context_Control_fp **fp_context_ptr
1116);
1117#endif
1118
1119/* XXX this should be possible to remove */
1120#if 0
1121/**
1122 * This routine restores the floating point context passed to it.
1123 *
1124 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1125 * point context area to restore
1126 *
1127 * @return on output @a *fp_context_ptr will contain the address that
1128 * should be used with @ref _CPU_Context_save_fp to save this context.
1129 *
1130 * Port Specific Information:
1131 *
1132 * XXX document implementation including references if appropriate
1133 */
1134void _CPU_Context_restore_fp(
1135  Context_Control_fp **fp_context_ptr
1136);
1137#endif
1138
1139static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1140{
1141  /* TODO */
1142}
1143
1144static inline void _CPU_Context_validate( uintptr_t pattern )
1145{
1146  while (1) {
1147    /* TODO */
1148  }
1149}
1150
1151/** @} */
1152
1153/* FIXME */
1154typedef CPU_Interrupt_frame CPU_Exception_frame;
1155
1156void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1157
1158/**
1159 * @ingroup CPUEndian
1160 * The following routine swaps the endian format of an unsigned int.
1161 * It must be static because it is referenced indirectly.
1162 *
1163 * This version will work on any processor, but if there is a better
1164 * way for your CPU PLEASE use it.  The most common way to do this is to:
1165 *
1166 *    swap least significant two bytes with 16-bit rotate
1167 *    swap upper and lower 16-bits
1168 *    swap most significant two bytes with 16-bit rotate
1169 *
1170 * Some CPUs have special instructions which swap a 32-bit quantity in
1171 * a single instruction (e.g. i486).  It is probably best to avoid
1172 * an "endian swapping control bit" in the CPU.  One good reason is
1173 * that interrupts would probably have to be disabled to ensure that
1174 * an interrupt does not try to access the same "chunk" with the wrong
1175 * endian.  Another good reason is that on some CPUs, the endian bit
1176 * endianness for ALL fetches -- both code and data -- so the code
1177 * will be fetched incorrectly.
1178 *
1179 * @param[in] value is the value to be swapped
1180 * @return the value after being endian swapped
1181 *
1182 * Port Specific Information:
1183 *
1184 * The v850 has a single instruction to swap endianness on a 32 bit quantity.
1185 */
1186static inline uint32_t CPU_swap_u32(
1187  uint32_t value
1188)
1189{
1190  unsigned int swapped;
1191
1192  #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
1193    unsigned int v;
1194
1195    v = value;
1196    __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) );
1197  #else
1198    uint32_t byte1, byte2, byte3, byte4;
1199
1200    byte4 = (value >> 24) & 0xff;
1201    byte3 = (value >> 16) & 0xff;
1202    byte2 = (value >> 8)  & 0xff;
1203    byte1 =  value        & 0xff;
1204
1205    swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1206  #endif
1207  return swapped;
1208}
1209
1210/**
1211 * @ingroup CPUEndian
1212 * This routine swaps a 16 bir quantity.
1213 *
1214 * @param[in] value is the value to be swapped
1215 * @return the value after being endian swapped
1216 *
1217 * Port Specific Information:
1218 *
1219 * The v850 has a single instruction to swap endianness on a 16 bit quantity.
1220 */
1221static inline uint16_t CPU_swap_u16( uint16_t value )
1222{
1223  unsigned int swapped;
1224
1225  #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1)
1226    unsigned int v;
1227
1228    v = value;
1229    __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) );
1230  #else
1231    swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff);
1232  #endif
1233  return swapped;
1234}
1235
1236typedef uint32_t CPU_Counter_ticks;
1237
1238CPU_Counter_ticks _CPU_Counter_read( void );
1239
1240static inline CPU_Counter_ticks _CPU_Counter_difference(
1241  CPU_Counter_ticks second,
1242  CPU_Counter_ticks first
1243)
1244{
1245  return second - first;
1246}
1247
1248#ifdef __cplusplus
1249}
1250#endif
1251
1252#endif
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