source: rtems/cpukit/score/cpu/v850/rtems/score/cpu.h @ 2d7ae960

4.115
Last change on this file since 2d7ae960 was 2d7ae960, checked in by Joel Sherrill <joel.sherrill@…>, on 06/11/12 at 18:37:29

v850 port: Initial addition with BSP for simulator in GDB

Port

+ v850 does not have appear to have any optimized bit scan instructions
+ v850 does have single instructions for wap u16 and u32
+ Code path optimization preferences set
+ Add BSP variants for each GCC CPU model flag and a README

  • v850e1 variant does not work (fails during BSP initialization)

BSP for GDB v850 Simulator

+ linkcmds matches defaults in GDB simulator with RTEMS mods
+ crt1.c added from v850 newlib port for main()
+ BSP exits cleanly
+ printk and console I/O work
+ uses clock tick from IDLE task
+ Tests not requiring real clock ISR work

Documentation

+ CPU Supplment chapter for v850 added

  • Property mode set to 100644
File size: 39.1 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the v850
7 *  processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2012.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/v850.h>
28
29/* conditional compilation parameters */
30
31/**
32 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
33 *
34 *  If TRUE, then they are inlined.
35 *  If FALSE, then a subroutine call is made.
36 *
37 *  This conditional is an example of the classic trade-off of size
38 *  versus speed.  Inlining the call (TRUE) typically increases the
39 *  size of RTEMS while speeding up the enabling of dispatching.
40 *
41 *  @note In general, the @ref _Thread_Dispatch_disable_level will
42 *  only be 0 or 1 unless you are in an interrupt handler and that
43 *  interrupt handler invokes the executive.]  When not inlined
44 *  something calls @ref _Thread_Enable_dispatch which in turns calls
45 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
46 *  one subroutine call is avoided entirely.
47 *
48 *  Port Specific Information:
49 *
50 *  The v850 is a RISC CPU which typically has enough memory to justify
51 *  the inlining of this method.
52 */
53#define CPU_INLINE_ENABLE_DISPATCH       TRUE
54
55/**
56 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
57 *  be unrolled one time?  In unrolled each iteration of the loop examines
58 *  two "nodes" on the chain being searched.  Otherwise, only one node
59 *  is examined per iteration.
60 *
61 *  If TRUE, then the loops are unrolled.
62 *  If FALSE, then the loops are not unrolled.
63 *
64 *  The primary factor in making this decision is the cost of disabling
65 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
66 *  body of the loop.  On some CPUs, the flash is more expensive than
67 *  one iteration of the loop body.  In this case, it might be desirable
68 *  to unroll the loop.  It is important to note that on some CPUs, this
69 *  code is the longest interrupt disable period in RTEMS.  So it is
70 *  necessary to strike a balance when setting this parameter.
71 *
72 *  Port Specific Information:
73 *
74 *  The v850 is a RISC CPU which typically has enough memory to justify
75 *  the unrolling of this method.
76 */
77#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
78
79/**
80 *  Does RTEMS manage a dedicated interrupt stack in software?
81 *
82 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
83 *  If FALSE, nothing is done.
84 *
85 *  If the CPU supports a dedicated interrupt stack in hardware,
86 *  then it is generally the responsibility of the BSP to allocate it
87 *  and set it up.
88 *
89 *  If the CPU does not support a dedicated interrupt stack, then
90 *  the porter has two options: (1) execute interrupts on the
91 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
92 *  interrupt stack.
93 *
94 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
95 *
96 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
97 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
98 *  possible that both are FALSE for a particular CPU.  Although it
99 *  is unclear what that would imply about the interrupt processing
100 *  procedure on that CPU.
101 *
102 *  Port Specific Information:
103 *
104 *  The v850 does not have support for a hardware interrupt stack.
105 */
106#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
107
108/**
109 *  Does the CPU follow the simple vectored interrupt model?
110 *
111 *  If TRUE, then RTEMS allocates the vector table it internally manages.
112 *  If FALSE, then the BSP is assumed to allocate and manage the vector
113 *  table
114 *
115 *  Port Specific Information:
116 *
117 *  This port uses the Progammable Interrupt Controller interrupt model.
118 */
119#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
120
121/**
122 *  Does this CPU have hardware support for a dedicated interrupt stack?
123 *
124 *  If TRUE, then it must be installed during initialization.
125 *  If FALSE, then no installation is performed.
126 *
127 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
128 *
129 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
130 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
131 *  possible that both are FALSE for a particular CPU.  Although it
132 *  is unclear what that would imply about the interrupt processing
133 *  procedure on that CPU.
134 *
135 *  Port Specific Information:
136 *
137 *  The v850 does not have support for a hardware interrupt stack.
138 */
139#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
140
141/**
142 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
143 *
144 *  If TRUE, then the memory is allocated during initialization.
145 *  If FALSE, then the memory is allocated during initialization.
146 *
147 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
148 *
149 *  Port Specific Information:
150 *
151 *  XXX document implementation including references if appropriate
152 */
153#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
154
155/**
156 *  @def CPU_HARDWARE_FP
157 *
158 *  Does the CPU have hardware floating point?
159 *
160 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
161 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
162 *
163 *  If there is a FP coprocessor such as the i387 or mc68881, then
164 *  the answer is TRUE.
165 *
166 *  The macro name "V850_HAS_FPU" should be made CPU specific.
167 *  It indicates whether or not this CPU model has FP support.  For
168 *  example, it would be possible to have an i386_nofp CPU model
169 *  which set this to false to indicate that you have an i386 without
170 *  an i387 and wish to leave floating point support out of RTEMS.
171 */
172
173/**
174 *  @def CPU_SOFTWARE_FP
175 *
176 *  Does the CPU have no hardware floating point and GCC provides a
177 *  software floating point implementation which must be context
178 *  switched?
179 *
180 *  This feature conditional is used to indicate whether or not there
181 *  is software implemented floating point that must be context
182 *  switched.  The determination of whether or not this applies
183 *  is very tool specific and the state saved/restored is also
184 *  compiler specific.
185 *
186 *  Port Specific Information:
187 *
188 *  Some v850 models do have IEEE hardware floating point support but
189 *  they do not have any special registers to save or bit(s) which
190 *  determine if the FPU is enabled. In short, there appears to be nothing
191 *  related to the floating point operations which impact the RTEMS
192 *  thread context switch. Thus from an RTEMS perspective, there is really
193 *  no FPU to manage.
194 */
195#define CPU_HARDWARE_FP     FALSE
196#define CPU_SOFTWARE_FP     FALSE
197
198/**
199 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
200 *
201 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
202 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
203 *
204 *  So far, the only CPUs in which this option has been used are the
205 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
206 *  gcc both implicitly used the floating point registers to perform
207 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
208 *  seen to allocate floating point local variables and touch the FPU
209 *  even when the flow through a subroutine (like vfprintf()) might
210 *  not use floating point formats.
211 *
212 *  If a function which you would not think utilize the FP unit DOES,
213 *  then one can not easily predict which tasks will use the FP hardware.
214 *  In this case, this option should be TRUE.
215 *
216 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
217 *
218 *  Port Specific Information:
219 *
220 *  This should be false until it has been demonstrated that gcc for the
221 *  v850 generates FPU code when it is unexpected. But even this would
222 *  not matter since there are no FP specific registers or bits which
223 *  would be corrupted if an FP operation occurred in an integer only
224 *  thread.
225 */
226#define CPU_ALL_TASKS_ARE_FP     FALSE
227
228/**
229 *  Should the IDLE task have a floating point context?
230 *
231 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
232 *  and it has a floating point context which is switched in and out.
233 *  If FALSE, then the IDLE task does not have a floating point context.
234 *
235 *  Setting this to TRUE negatively impacts the time required to preempt
236 *  the IDLE task from an interrupt because the floating point context
237 *  must be saved as part of the preemption.
238 *
239 *  Port Specific Information:
240 *
241 *  The IDLE thread should not be using the FPU. Leave this off.
242 */
243#define CPU_IDLE_TASK_IS_FP      FALSE
244
245/**
246 *  Should the saving of the floating point registers be deferred
247 *  until a context switch is made to another different floating point
248 *  task?
249 *
250 *  If TRUE, then the floating point context will not be stored until
251 *  necessary.  It will remain in the floating point registers and not
252 *  disturned until another floating point task is switched to.
253 *
254 *  If FALSE, then the floating point context is saved when a floating
255 *  point task is switched out and restored when the next floating point
256 *  task is restored.  The state of the floating point registers between
257 *  those two operations is not specified.
258 *
259 *  If the floating point context does NOT have to be saved as part of
260 *  interrupt dispatching, then it should be safe to set this to TRUE.
261 *
262 *  Setting this flag to TRUE results in using a different algorithm
263 *  for deciding when to save and restore the floating point context.
264 *  The deferred FP switch algorithm minimizes the number of times
265 *  the FP context is saved and restored.  The FP context is not saved
266 *  until a context switch is made to another, different FP task.
267 *  Thus in a system with only one FP task, the FP context will never
268 *  be saved or restored.
269 *
270 *  Port Specific Information:
271 *
272 *  See earlier comments. There is no FPU state to manage.
273 */
274#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
275
276/**
277 *  Does this port provide a CPU dependent IDLE task implementation?
278 *
279 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
280 *  must be provided and is the default IDLE thread body instead of
281 *  @ref _CPU_Thread_Idle_body.
282 *
283 *  If FALSE, then use the generic IDLE thread body if the BSP does
284 *  not provide one.
285 *
286 *  This is intended to allow for supporting processors which have
287 *  a low power or idle mode.  When the IDLE thread is executed, then
288 *  the CPU can be powered down.
289 *
290 *  The order of precedence for selecting the IDLE thread body is:
291 *
292 *    -#  BSP provided
293 *    -#  CPU dependent (if provided)
294 *    -#  generic (if no BSP and no CPU dependent)
295 *
296 *  Port Specific Information:
297 *
298 *  There does not appear to be a reason for the v850 port itself to provide
299 *  a special idle task.
300 */
301#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
302
303/**
304 *  Does the stack grow up (toward higher addresses) or down
305 *  (toward lower addresses)?
306 *
307 *  If TRUE, then the grows upward.
308 *  If FALSE, then the grows toward smaller addresses.
309 *
310 *  Port Specific Information:
311 *
312 *  The v850 stack grows from high addresses to low addresses.
313 */
314#define CPU_STACK_GROWS_UP               FALSE
315
316/**
317 *  The following is the variable attribute used to force alignment
318 *  of critical RTEMS structures.  On some processors it may make
319 *  sense to have these aligned on tighter boundaries than
320 *  the minimum requirements of the compiler in order to have as
321 *  much of the critical data area as possible in a cache line.
322 *
323 *  The placement of this macro in the declaration of the variables
324 *  is based on the syntactically requirements of the GNU C
325 *  "__attribute__" extension.  For example with GNU C, use
326 *  the following to force a structures to a 32 byte boundary.
327 *
328 *      __attribute__ ((aligned (32)))
329 *
330 *  @note Currently only the Priority Bit Map table uses this feature.
331 *        To benefit from using this, the data must be heavily
332 *        used so it will stay in the cache and used frequently enough
333 *        in the executive to justify turning this on.
334 *
335 *  Port Specific Information:
336 *
337 *  Until proven otherwise, use the compiler default.
338 */
339#define CPU_STRUCTURE_ALIGNMENT
340
341/**
342 *  The v850 should use 64-bit timestamps and inline them.
343 */
344#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
345
346/**
347 *  @defgroup CPUEndian Processor Dependent Endianness Support
348 *
349 *  This group assists in issues related to processor endianness.
350 */
351
352/**
353 *  @ingroup CPUEndian
354 *  Define what is required to specify how the network to host conversion
355 *  routines are handled.
356 *
357 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
358 *  same values.
359 *
360 *  @see CPU_LITTLE_ENDIAN
361 *
362 *  Port Specific Information:
363 *
364 *  The v850 is little endian.
365 */
366#define CPU_BIG_ENDIAN  FALSE
367
368/**
369 *  @ingroup CPUEndian
370 *  Define what is required to specify how the network to host conversion
371 *  routines are handled.
372 *
373 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
374 *  same values.
375 *
376 *  @see CPU_BIG_ENDIAN
377 *
378 *  Port Specific Information:
379 *
380 *  The v850 is little endian.
381 */
382#define CPU_LITTLE_ENDIAN TRUE
383
384/**
385 *  @ingroup CPUInterrupt
386 *  The following defines the number of bits actually used in the
387 *  interrupt field of the task mode.  How those bits map to the
388 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
389 *
390 *  Port Specific Information:
391 *
392 *  The v850 only has a single bit in the CPU for interrupt disable/enable.
393 */
394#define CPU_MODES_INTERRUPT_MASK   0x00000001
395
396/**
397 * @defgroup CPUContext Processor Dependent Context Management
398 *
399 *  From the highest level viewpoint, there are 2 types of context to save.
400 *
401 *     -# Interrupt registers to save
402 *     -# Task level registers to save
403 *
404 *  Since RTEMS handles integer and floating point contexts separately, this
405 *  means we have the following 3 context items:
406 *
407 *     -# task level context stuff::  Context_Control
408 *     -# floating point task stuff:: Context_Control_fp
409 *     -# special interrupt level context :: CPU_Interrupt_frame
410 *
411 *  On some processors, it is cost-effective to save only the callee
412 *  preserved registers during a task context switch.  This means
413 *  that the ISR code needs to save those registers which do not
414 *  persist across function calls.  It is not mandatory to make this
415 *  distinctions between the caller/callee saves registers for the
416 *  purpose of minimizing context saved during task switch and on interrupts.
417 *  If the cost of saving extra registers is minimal, simplicity is the
418 *  choice.  Save the same context on interrupt entry as for tasks in
419 *  this case.
420 *
421 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
422 *  care should be used in designing the context area.
423 *
424 *  On some CPUs with hardware floating point support, the Context_Control_fp
425 *  structure will not be used or it simply consist of an array of a
426 *  fixed number of bytes.   This is done when the floating point context
427 *  is dumped by a "FP save context" type instruction and the format
428 *  is not really defined by the CPU.  In this case, there is no need
429 *  to figure out the exact format -- only the size.  Of course, although
430 *  this is enough information for RTEMS, it is probably not enough for
431 *  a debugger such as gdb.  But that is another problem.
432 *
433 *  Port Specific Information:
434 *
435 *  On the v850, this port saves special registers and those that are
436 *  callee saved.
437 */
438
439/**
440 *  @ingroup CPUContext Management
441 *  This defines the minimal set of integer and processor state registers
442 *  that must be saved during a voluntary context switch from one thread
443 *  to another.
444 */
445typedef struct {
446    uint32_t   r1;
447    /** This field is the stack pointer (e.g. r3).  */
448    uint32_t   r3_stack_pointer;
449    uint32_t   r20;
450    uint32_t   r21;
451    uint32_t   r22;
452    uint32_t   r23;
453    uint32_t   r24;
454    uint32_t   r25;
455    uint32_t   r26;
456    uint32_t   r27;
457    uint32_t   r28;
458    uint32_t   r29;
459    uint32_t   r31;
460    uint32_t   psw;
461} Context_Control;
462
463/**
464 *  @ingroup CPUContext Management
465 *
466 *  This macro returns the stack pointer associated with @a _context.
467 *
468 *  @param[in] _context is the thread context area to access
469 *
470 *  @return This method returns the stack pointer.
471 */
472#define _CPU_Context_Get_SP( _context ) \
473  (_context)->r3_stack_pointer
474
475/**
476 *  @ingroup CPUContext Management
477 *  This defines the complete set of floating point registers that must
478 *  be saved during any context switch from one thread to another.
479 */
480typedef struct {
481    /** FPU registers are listed here */
482    double      some_float_register;
483} Context_Control_fp;
484
485/**
486 *  @ingroup CPUContext Management
487 *  This defines the set of integer and processor state registers that must
488 *  be saved during an interrupt.  This set does not include any which are
489 *  in @ref Context_Control.
490 */
491typedef struct {
492    /** This field is a hint that a port will have a number of integer
493     *  registers that need to be saved when an interrupt occurs or
494     *  when a context switch occurs at the end of an ISR.
495     */
496    uint32_t   special_interrupt_register;
497} CPU_Interrupt_frame;
498
499/**
500 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
501 *
502 *  On some CPUs, RTEMS supports a software managed interrupt stack.
503 *  This stack is allocated by the Interrupt Manager and the switch
504 *  is performed in @ref _ISR_Handler.  These variables contain pointers
505 *  to the lowest and highest addresses in the chunk of memory allocated
506 *  for the interrupt stack.  Since it is unknown whether the stack
507 *  grows up or down (in general), this give the CPU dependent
508 *  code the option of picking the version it wants to use.
509 *
510 *  @note These two variables are required if the macro
511 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
512 *
513 *  Port Specific Information:
514 *
515 *  XXX document implementation including references if appropriate
516 */
517
518/**
519 *  @ingroup CPUContext
520 *  The size of the floating point context area.  On some CPUs this
521 *  will not be a "sizeof" because the format of the floating point
522 *  area is not defined -- only the size is.  This is usually on
523 *  CPUs with a "floating point save context" instruction.
524 *
525 *  Port Specific Information:
526 *
527 *  The v850 does not need a floating point context but this needs to be
528 *  defined so confdefs.h.
529 */
530/* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */
531#define CPU_CONTEXT_FP_SIZE 0
532
533/**
534 *  Amount of extra stack (above minimum stack size) required by
535 *  MPCI receive server thread.  Remember that in a multiprocessor
536 *  system this thread must exist and be able to process all directives.
537 *
538 *  Port Specific Information:
539 *
540 *  There is no reason to think the v850 needs extra MPCI receive
541 *  server stack.
542 */
543#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
544
545/* XXX this should not be needed on PIC architectures */
546/* XXX evaluate removing it */
547#if 0
548/**
549 *  @ingroup CPUInterrupt
550 *  This defines the number of entries in the @ref _ISR_Vector_table managed
551 *  by RTEMS.
552 *
553 *  Port Specific Information:
554 *
555 *  XXX document implementation including references if appropriate
556 */
557#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
558#endif
559
560/**
561 *  @ingroup CPUInterrupt
562 *  This defines the highest interrupt vector number for this port.
563 */
564#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
565
566/**
567 *  @ingroup CPUInterrupt
568 *  This is defined if the port has a special way to report the ISR nesting
569 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
570 */
571#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
572
573/**
574 *  @ingroup CPUContext
575 *  Should be large enough to run all RTEMS tests.  This ensures
576 *  that a "reasonable" small application should not have any problems.
577 *
578 *  Port Specific Information:
579 *
580 *  This should be very conservative on the v850.
581 */
582#define CPU_STACK_MINIMUM_SIZE          (1024*4)
583
584/**
585 *  CPU's worst alignment requirement for data types on a byte boundary.  This
586 *  alignment does not take into account the requirements for the stack.
587 *
588 *  Port Specific Information:
589 *
590 *  There is no apparent reason why this should be larger than 8.
591 */
592#define CPU_ALIGNMENT              8
593
594/**
595 *  This number corresponds to the byte alignment requirement for the
596 *  heap handler.  This alignment requirement may be stricter than that
597 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
598 *  common for the heap to follow the same alignment requirement as
599 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
600 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
601 *
602 *  @note  This does not have to be a power of 2 although it should be
603 *         a multiple of 2 greater than or equal to 2.  The requirement
604 *         to be a multiple of 2 is because the heap uses the least
605 *         significant field of the front and back flags to indicate
606 *         that a block is in use or free.  So you do not want any odd
607 *         length blocks really putting length data in that bit.
608 *
609 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
610 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
611 *         elements allocated from the heap meet all restrictions.
612 *
613 *  Port Specific Information:
614 *
615 *  There is no apparent reason why this should be larger than CPU_ALIGNMENT.
616 */
617#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
618
619/**
620 *  This number corresponds to the byte alignment requirement for memory
621 *  buffers allocated by the partition manager.  This alignment requirement
622 *  may be stricter than that for the data types alignment specified by
623 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
624 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
625 *  strict enough for the partition, then this should be set to
626 *  @ref CPU_ALIGNMENT.
627 *
628 *  @note  This does not have to be a power of 2.  It does have to
629 *         be greater or equal to than @ref CPU_ALIGNMENT.
630 *
631 *  Port Specific Information:
632 *
633 *  There is no apparent reason why this should be larger than CPU_ALIGNMENT.
634 */
635#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
636
637/**
638 *  This number corresponds to the byte alignment requirement for the
639 *  stack.  This alignment requirement may be stricter than that for the
640 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
641 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
642 *  set to 0.
643 *
644 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
645 *
646 *  Port Specific Information:
647 *
648 *  The v850 has enough RAM where alignment to 16 may be desirable depending
649 *  on the cache properties. But this remains to be demonstrated.
650 */
651#define CPU_STACK_ALIGNMENT        4
652
653/*
654 *  ISR handler macros
655 */
656
657/**
658 *  @ingroup CPUInterrupt
659 *  Disable all interrupts for an RTEMS critical section.  The previous
660 *  level is returned in @a _isr_cookie.
661 *
662 *  @param[out] _isr_cookie will contain the previous level cookie
663 *
664 *  Port Specific Information:
665 *
666 *  On the v850, we need to save the PSW and use "di" to disable interrupts.
667 */
668#define _CPU_ISR_Disable( _isr_cookie ) \
669  do { \
670    unsigned int _psw; \
671    \
672    v850_get_psw( _psw ); \
673    __asm__ __volatile__( "di" ); \
674    _isr_cookie = _psw; \
675  } while (0)
676
677/**
678 *  @ingroup CPUInterrupt
679 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
680 *  This indicates the end of an RTEMS critical section.  The parameter
681 *  @a _isr_cookie is not modified.
682 *
683 *  @param[in] _isr_cookie contain the previous level cookie
684 *
685 *  Port Specific Information:
686 *
687 *  On the v850, we simply need to restore the PSW.
688 */
689#define _CPU_ISR_Enable( _isr_cookie )  \
690  do { \
691    unsigned int _psw = (_isr_cookie); \
692    \
693    v850_set_psw( _psw ); \
694  } while (0)
695
696/**
697 *  @ingroup CPUInterrupt
698 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
699 *  disabling them again.  This is used to divide long RTEMS critical
700 *  sections into two or more parts.  The parameter @a _isr_cookie is not
701 *  modified.
702 *
703 *  @param[in] _isr_cookie contain the previous level cookie
704 *
705 *  Port Specific Information:
706 *
707 *  This saves at least one instruction over using enable/disable back to back.
708 */
709#define _CPU_ISR_Flash( _isr_cookie ) \
710  do { \
711    unsigned int _psw = (_isr_cookie); \
712    v850_set_psw( _psw ); \
713    __asm__ __volatile__( "di" ); \
714  } while (0)
715
716/**
717 *  @ingroup CPUInterrupt
718 *
719 *  This routine and @ref _CPU_ISR_Get_level
720 *  Map the interrupt level in task mode onto the hardware that the CPU
721 *  actually provides.  Currently, interrupt levels which do not
722 *  map onto the CPU in a generic fashion are undefined.  Someday,
723 *  it would be nice if these were "mapped" by the application
724 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
725 *  8 - 255 would be available for bsp/application specific meaning.
726 *  This could be used to manage a programmable interrupt controller
727 *  via the rtems_task_mode directive.
728 *
729 *  Port Specific Information:
730 *
731 *  On the v850, level 0 is enabled. Non-zero is disabled.
732 */
733#define _CPU_ISR_Set_level( new_level ) \
734  do { \
735    if ( new_level ) \
736      __asm__ __volatile__( "di" ); \
737    else \
738      __asm__ __volatile__( "ei" ); \
739  } while (0)
740
741/**
742 *  @ingroup CPUInterrupt
743 *  Return the current interrupt disable level for this task in
744 *  the format used by the interrupt level portion of the task mode.
745 *
746 *  @note This routine usually must be implemented as a subroutine.
747 *
748 *  Port Specific Information:
749 *
750 *  This method is implemented in C on the v850.
751 */
752uint32_t   _CPU_ISR_Get_level( void );
753
754/* end of ISR handler macros */
755
756/* Context handler macros */
757
758/**
759 *  @ingroup CPUContext
760 *  Initialize the context to a state suitable for starting a
761 *  task after a context restore operation.  Generally, this
762 *  involves:
763 *
764 *     - setting a starting address
765 *     - preparing the stack
766 *     - preparing the stack and frame pointers
767 *     - setting the proper interrupt level in the context
768 *     - initializing the floating point context
769 *
770 *  This routine generally does not set any unnecessary register
771 *  in the context.  The state of the "general data" registers is
772 *  undefined at task start time.
773 *
774 *  @param[in] _the_context is the context structure to be initialized
775 *  @param[in] _stack_base is the lowest physical address of this task's stack
776 *  @param[in] _size is the size of this task's stack
777 *  @param[in] _isr is the interrupt disable level
778 *  @param[in] _entry_point is the thread's entry point.  This is
779 *         always @a _Thread_Handler
780 *  @param[in] _is_fp is TRUE if the thread is to be a floating
781 *        point thread.  This is typically only used on CPUs where the
782 *        FPU may be easily disabled by software such as on the SPARC
783 *        where the PSR contains an enable FPU bit.
784 *
785 *  Port Specific Information:
786 *
787 *  This method is implemented in C on the v850.
788 */
789void _CPU_Context_Initialize(
790  Context_Control  *the_context,
791  uint32_t         *stack_base,
792  uint32_t          size,
793  uint32_t          new_level,
794  void             *entry_point,
795  bool              is_fp
796);
797
798/**
799 *  This routine is responsible for somehow restarting the currently
800 *  executing task.  If you are lucky, then all that is necessary
801 *  is restoring the context.  Otherwise, there will need to be
802 *  a special assembly routine which does something special in this
803 *  case.  For many ports, simply adding a label to the restore path
804 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
805 *  possibly to load a few arguments and jump to the restore path. It will
806 *  not work if restarting self conflicts with the stack frame
807 *  assumptions of restoring a context.
808 *
809 *  Port Specific Information:
810 *
811 *  On the v850, we require a special entry point to restart a task.
812 */
813#define _CPU_Context_Restart_self( _the_context ) \
814   _CPU_Context_restore( (_the_context) );
815
816/* XXX this should be possible to remove */
817#if 0
818/**
819 *  @ingroup CPUContext
820 *  The purpose of this macro is to allow the initial pointer into
821 *  a floating point context area (used to save the floating point
822 *  context) to be at an arbitrary place in the floating point
823 *  context area.
824 *
825 *  This is necessary because some FP units are designed to have
826 *  their context saved as a stack which grows into lower addresses.
827 *  Other FP units can be saved by simply moving registers into offsets
828 *  from the base of the context area.  Finally some FP units provide
829 *  a "dump context" instruction which could fill in from high to low
830 *  or low to high based on the whim of the CPU designers.
831 *
832 *  @param[in] _base is the lowest physical address of the floating point
833 *         context area
834 *  @param[in] _offset is the offset into the floating point area
835 *
836 *  Port Specific Information:
837 *
838 *  XXX document implementation including references if appropriate
839 */
840#define _CPU_Context_Fp_start( _base, _offset ) \
841   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
842#endif
843
844/* XXX this should be possible to remove */
845#if 0
846/**
847 *  This routine initializes the FP context area passed to it to.
848 *  There are a few standard ways in which to initialize the
849 *  floating point context.  The code included for this macro assumes
850 *  that this is a CPU in which a "initial" FP context was saved into
851 *  @a _CPU_Null_fp_context and it simply copies it to the destination
852 *  context passed to it.
853 *
854 *  Other floating point context save/restore models include:
855 *    -# not doing anything, and
856 *    -# putting a "null FP status word" in the correct place in the FP context.
857 *
858 *  @param[in] _destination is the floating point context area
859 *
860 *  Port Specific Information:
861 *
862 *  XXX document implementation including references if appropriate
863 */
864#define _CPU_Context_Initialize_fp( _destination ) \
865  { \
866  }
867#endif
868
869/* end of Context handler macros */
870
871/* Fatal Error manager macros */
872
873/**
874 *  This routine copies _error into a known place -- typically a stack
875 *  location or a register, optionally disables interrupts, and
876 *  halts/stops the CPU.
877 *
878 *  Port Specific Information:
879 *
880 *  Move the error code into r10, disable interrupts and halt.
881 */
882#define _CPU_Fatal_halt( _error ) \
883  do { \
884    __asm__ __volatile__ ( "di" ); \
885    __asm__ __volatile__ ( "mov %0, r10; " : "=r" ((_error)) ); \
886    __asm__ __volatile__ ( "halt" ); \
887  } while (0)
888
889/* end of Fatal Error manager macros */
890
891/* Bitfield handler macros */
892
893/**
894 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
895 *
896 *  This set of routines are used to implement fast searches for
897 *  the most important ready task.
898 */
899
900/**
901 *  @ingroup CPUBitfield
902 *  This definition is set to TRUE if the port uses the generic bitfield
903 *  manipulation implementation.
904 */
905#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
906
907/**
908 *  @ingroup CPUBitfield
909 *  This definition is set to TRUE if the port uses the data tables provided
910 *  by the generic bitfield manipulation implementation.
911 *  This can occur when actually using the generic bitfield manipulation
912 *  implementation or when implementing the same algorithm in assembly
913 *  language for improved performance.  It is unlikely that a port will use
914 *  the data if it has a bitfield scan instruction.
915 *
916 *  Port Specific Information:
917 *
918 *  There is no single v850 instruction to do a bit scan so there is
919 *  no CPU specific implementation of bit field scanning. The empty
920 *  stub routines are left as a place holder in case someone figures
921 *  out how to do a v850 implementation better than the generic algorithm.
922 */
923#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
924
925/**
926 *  @ingroup CPUBitfield
927 *  This routine sets @a _output to the bit number of the first bit
928 *  set in @a _value.  @a _value is of CPU dependent type
929 *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
930 *  wide although only the 16 least significant bits will be used.
931 *
932 *  There are a number of variables in using a "find first bit" type
933 *  instruction.
934 *
935 *    -# What happens when run on a value of zero?
936 *    -# Bits may be numbered from MSB to LSB or vice-versa.
937 *    -# The numbering may be zero or one based.
938 *    -# The "find first bit" instruction may search from MSB or LSB.
939 *
940 *  RTEMS guarantees that (1) will never happen so it is not a concern.
941 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
942 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
943 *  which must logically operate together.  Bits in the _value are
944 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
945 *  The basic major and minor values calculated by @ref _Priority_Major
946 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
947 *  to properly range between the values returned by the "find first bit"
948 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
949 *  calculate the major and directly index into the minor table.
950 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
951 *  is the first bit found.
952 *
953 *  This entire "find first bit" and mapping process depends heavily
954 *  on the manner in which a priority is broken into a major and minor
955 *  components with the major being the 4 MSB of a priority and minor
956 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
957 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
958 *  to the lowest priority.
959 *
960 *  If your CPU does not have a "find first bit" instruction, then
961 *  there are ways to make do without it.  Here are a handful of ways
962 *  to implement this in software:
963 *
964@verbatim
965      - a series of 16 bit test instructions
966      - a "binary search using if's"
967      - _number = 0
968        if _value > 0x00ff
969          _value >>=8
970          _number = 8;
971
972        if _value > 0x0000f
973          _value >=8
974          _number += 4
975
976        _number += bit_set_table[ _value ]
977@endverbatim
978
979 *    where bit_set_table[ 16 ] has values which indicate the first
980 *      bit set
981 *
982 *  @param[in] _value is the value to be scanned
983 *  @param[in] _output is the first bit set
984 *
985 *  Port Specific Information:
986 *
987 *  There is no single v850 instruction to do a bit scan so there is
988 *  no CPU specific implementation of bit field scanning.
989 */
990#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
991#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
992  { \
993    (_output) = 0;   /* do something to prevent warnings */ \
994  }
995#endif
996
997/* end of Bitfield handler macros */
998
999/**
1000 *  This routine builds the mask which corresponds to the bit fields
1001 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1002 *  for that routine.
1003 *
1004 *  Port Specific Information:
1005 *
1006 *  There is no single v850 instruction to do a bit scan so there is
1007 *  no CPU specific implementation of bit field scanning.
1008 */
1009#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1010
1011#define _CPU_Priority_Mask( _bit_number ) \
1012  ( 1 << (_bit_number) )
1013
1014#endif
1015
1016/**
1017 *  @ingroup CPUBitfield
1018 *  This routine translates the bit numbers returned by
1019 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1020 *  a major or minor component of a priority.  See the discussion
1021 *  for that routine.
1022 *
1023 *  @param[in] _priority is the major or minor number to translate
1024 *
1025 *  Port Specific Information:
1026 *
1027 *  There is no single v850 instruction to do a bit scan so there is
1028 *  no CPU specific implementation of bit field scanning.
1029 */
1030#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1031
1032#define _CPU_Priority_bits_index( _priority ) \
1033  (_priority)
1034
1035#endif
1036
1037/* end of Priority handler macros */
1038
1039/* functions */
1040
1041/**
1042 *  This routine performs CPU dependent initialization.
1043 *
1044 *  Port Specific Information:
1045 *
1046 *  This is implemented in C.
1047 */
1048void _CPU_Initialize(void);
1049
1050/**
1051 *  @ingroup CPUContext
1052 *  This routine switches from the run context to the heir context.
1053 *
1054 *  @param[in] run points to the context of the currently executing task
1055 *  @param[in] heir points to the context of the heir task
1056 *
1057 *  Port Specific Information:
1058 *
1059 *  This is implemented in assembly on the v850.
1060 */
1061void _CPU_Context_switch(
1062  Context_Control  *run,
1063  Context_Control  *heir
1064);
1065
1066/**
1067 *  @ingroup CPUContext
1068 *  This routine is generally used only to restart self in an
1069 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1070 *
1071 *  @param[in] new_context points to the context to be restored.
1072 *
1073 *  @note May be unnecessary to reload some registers.
1074 *
1075 *  Port Specific Information:
1076 *
1077 *  This is implemented in assembly on the v850.
1078 */
1079void _CPU_Context_restore(
1080  Context_Control *new_context
1081) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1082
1083/* XXX this should be possible to remove */
1084#if 0
1085/**
1086 *  @ingroup CPUContext
1087 *  This routine saves the floating point context passed to it.
1088 *
1089 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1090 *  point context area
1091 *
1092 *  @return on output @a *fp_context_ptr will contain the address that
1093 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1094 *
1095 *  Port Specific Information:
1096 *
1097 *  XXX document implementation including references if appropriate
1098 */
1099void _CPU_Context_save_fp(
1100  Context_Control_fp **fp_context_ptr
1101);
1102#endif
1103
1104/* XXX this should be possible to remove */
1105#if 0
1106/**
1107 *  @ingroup CPUContext
1108 *  This routine restores the floating point context passed to it.
1109 *
1110 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1111 *  point context area to restore
1112 *
1113 *  @return on output @a *fp_context_ptr will contain the address that
1114 *  should be used with @ref _CPU_Context_save_fp to save this context.
1115 *
1116 *  Port Specific Information:
1117 *
1118 *  XXX document implementation including references if appropriate
1119 */
1120void _CPU_Context_restore_fp(
1121  Context_Control_fp **fp_context_ptr
1122);
1123#endif
1124
1125/**
1126 *  @ingroup CPUEndian
1127 *  The following routine swaps the endian format of an unsigned int.
1128 *  It must be static because it is referenced indirectly.
1129 *
1130 *  This version will work on any processor, but if there is a better
1131 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1132 *
1133 *     swap least significant two bytes with 16-bit rotate
1134 *     swap upper and lower 16-bits
1135 *     swap most significant two bytes with 16-bit rotate
1136 *
1137 *  Some CPUs have special instructions which swap a 32-bit quantity in
1138 *  a single instruction (e.g. i486).  It is probably best to avoid
1139 *  an "endian swapping control bit" in the CPU.  One good reason is
1140 *  that interrupts would probably have to be disabled to ensure that
1141 *  an interrupt does not try to access the same "chunk" with the wrong
1142 *  endian.  Another good reason is that on some CPUs, the endian bit
1143 *  endianness for ALL fetches -- both code and data -- so the code
1144 *  will be fetched incorrectly.
1145 *
1146 *  @param[in] value is the value to be swapped
1147 *  @return the value after being endian swapped
1148 *
1149 *  Port Specific Information:
1150 *
1151 *  The v850 has a single instruction to swap endianness on a 32 bit quantity.
1152 */
1153static inline uint32_t CPU_swap_u32(
1154  uint32_t value
1155)
1156{
1157  unsigned int v, swapped;
1158
1159  v = value;
1160  __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) );
1161  return swapped;
1162}
1163
1164/**
1165 *  @ingroup CPUEndian
1166 *  This routine swaps a 16 bir quantity.
1167 *
1168 *  @param[in] value is the value to be swapped
1169 *  @return the value after being endian swapped
1170 *
1171 *  Port Specific Information:
1172 *
1173 *  The v850 has a single instruction to swap endianness on a 16 bit quantity.
1174 */
1175static inline uint16_t CPU_swap_u16( uint16_t value )
1176{
1177  unsigned int v, swapped;
1178
1179  v = value;
1180  __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) );
1181  return swapped;
1182}
1183
1184#ifdef __cplusplus
1185}
1186#endif
1187
1188#endif
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