1 | /* SPDX-License-Identifier: BSD-2-Clause */ |
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2 | |
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3 | /** |
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4 | * @file |
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5 | * |
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6 | * @brief V850 CPU Department Source |
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7 | * |
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8 | * This include file contains information pertaining to the v850 |
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9 | * processor. |
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10 | */ |
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11 | |
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12 | /* |
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13 | * COPYRIGHT (c) 1989-2012. |
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14 | * On-Line Applications Research Corporation (OAR). |
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15 | * |
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16 | * Redistribution and use in source and binary forms, with or without |
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17 | * modification, are permitted provided that the following conditions |
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18 | * are met: |
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19 | * 1. Redistributions of source code must retain the above copyright |
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20 | * notice, this list of conditions and the following disclaimer. |
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21 | * 2. Redistributions in binary form must reproduce the above copyright |
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22 | * notice, this list of conditions and the following disclaimer in the |
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23 | * documentation and/or other materials provided with the distribution. |
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24 | * |
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25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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28 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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29 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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30 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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31 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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32 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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33 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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34 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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35 | * POSSIBILITY OF SUCH DAMAGE. |
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36 | */ |
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37 | |
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38 | #ifndef _RTEMS_SCORE_CPU_H |
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39 | #define _RTEMS_SCORE_CPU_H |
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40 | |
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41 | #ifdef __cplusplus |
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42 | extern "C" { |
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43 | #endif |
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44 | |
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45 | #include <rtems/score/basedefs.h> |
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46 | #include <rtems/score/v850.h> |
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47 | |
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48 | /* conditional compilation parameters */ |
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49 | |
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50 | /** |
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51 | * Does the CPU follow the simple vectored interrupt model? |
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52 | * |
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53 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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54 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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55 | * table |
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56 | * |
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57 | * Port Specific Information: |
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58 | * |
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59 | * This port uses the Progammable Interrupt Controller interrupt model. |
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60 | */ |
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61 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
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62 | |
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63 | #define CPU_HARDWARE_FP FALSE |
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64 | |
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65 | #define CPU_SOFTWARE_FP FALSE |
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66 | |
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67 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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68 | |
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69 | #define CPU_IDLE_TASK_IS_FP FALSE |
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70 | |
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71 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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72 | |
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73 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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74 | |
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75 | /** |
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76 | * Does the stack grow up (toward higher addresses) or down |
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77 | * (toward lower addresses)? |
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78 | * |
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79 | * If TRUE, then the grows upward. |
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80 | * If FALSE, then the grows toward smaller addresses. |
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81 | * |
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82 | * Port Specific Information: |
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83 | * |
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84 | * The v850 stack grows from high addresses to low addresses. |
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85 | */ |
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86 | #define CPU_STACK_GROWS_UP FALSE |
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87 | |
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88 | /* FIXME: Is this the right value? */ |
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89 | #define CPU_CACHE_LINE_BYTES 32 |
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90 | |
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91 | #define CPU_STRUCTURE_ALIGNMENT |
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92 | |
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93 | /** |
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94 | * @addtogroup RTEMSScoreCPUV850CPUInterrupt |
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95 | * The following defines the number of bits actually used in the |
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96 | * interrupt field of the task mode. How those bits map to the |
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97 | * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. |
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98 | * |
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99 | * Port Specific Information: |
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100 | * |
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101 | * The v850 only has a single bit in the CPU for interrupt disable/enable. |
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102 | */ |
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103 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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104 | |
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105 | #define CPU_MAXIMUM_PROCESSORS 32 |
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106 | |
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107 | /** |
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108 | * @defgroup RTEMSScoreCPUV850CPUContext Processor Dependent Context Management |
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109 | * |
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110 | * @ingroup RTEMSScoreCPUV850 |
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111 | * |
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112 | * From the highest level viewpoint, there are 2 types of context to save. |
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113 | * |
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114 | * -# Interrupt registers to save |
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115 | * -# Task level registers to save |
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116 | * |
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117 | * Since RTEMS handles integer and floating point contexts separately, this |
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118 | * means we have the following 3 context items: |
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119 | * |
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120 | * -# task level context stuff:: Context_Control |
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121 | * -# floating point task stuff:: Context_Control_fp |
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122 | * -# special interrupt level context :: CPU_Interrupt_frame |
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123 | * |
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124 | * On some processors, it is cost-effective to save only the callee |
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125 | * preserved registers during a task context switch. This means |
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126 | * that the ISR code needs to save those registers which do not |
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127 | * persist across function calls. It is not mandatory to make this |
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128 | * distinctions between the caller/callee saves registers for the |
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129 | * purpose of minimizing context saved during task switch and on interrupts. |
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130 | * If the cost of saving extra registers is minimal, simplicity is the |
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131 | * choice. Save the same context on interrupt entry as for tasks in |
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132 | * this case. |
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133 | * |
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134 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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135 | * care should be used in designing the context area. |
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136 | * |
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137 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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138 | * structure will not be used or it simply consist of an array of a |
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139 | * fixed number of bytes. This is done when the floating point context |
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140 | * is dumped by a "FP save context" type instruction and the format |
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141 | * is not really defined by the CPU. In this case, there is no need |
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142 | * to figure out the exact format -- only the size. Of course, although |
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143 | * this is enough information for RTEMS, it is probably not enough for |
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144 | * a debugger such as gdb. But that is another problem. |
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145 | * |
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146 | * Port Specific Information: |
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147 | * |
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148 | * On the v850, this port saves special registers and those that are |
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149 | * callee saved. |
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150 | */ |
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151 | /** @{ **/ |
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152 | |
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153 | /** |
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154 | * This defines the minimal set of integer and processor state registers |
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155 | * that must be saved during a voluntary context switch from one thread |
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156 | * to another. |
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157 | */ |
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158 | typedef struct { |
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159 | uint32_t r1; |
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160 | /** This field is the stack pointer (e.g. r3). */ |
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161 | uint32_t r3_stack_pointer; |
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162 | uint32_t r20; |
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163 | uint32_t r21; |
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164 | uint32_t r22; |
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165 | uint32_t r23; |
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166 | uint32_t r24; |
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167 | uint32_t r25; |
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168 | uint32_t r26; |
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169 | uint32_t r27; |
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170 | uint32_t r28; |
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171 | uint32_t r29; |
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172 | uint32_t r31; |
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173 | uint32_t psw; |
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174 | } Context_Control; |
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175 | |
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176 | /** |
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177 | * This macro returns the stack pointer associated with @a _context. |
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178 | * |
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179 | * @param[in] _context is the thread context area to access |
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180 | * |
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181 | * @return This method returns the stack pointer. |
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182 | */ |
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183 | #define _CPU_Context_Get_SP( _context ) \ |
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184 | (_context)->r3_stack_pointer |
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185 | |
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186 | /** |
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187 | * This defines the set of integer and processor state registers that must |
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188 | * be saved during an interrupt. This set does not include any which are |
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189 | * in @ref Context_Control. |
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190 | */ |
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191 | typedef struct { |
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192 | /** This field is a hint that a port will have a number of integer |
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193 | * registers that need to be saved when an interrupt occurs or |
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194 | * when a context switch occurs at the end of an ISR. |
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195 | */ |
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196 | uint32_t special_interrupt_register; |
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197 | } CPU_Interrupt_frame; |
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198 | |
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199 | /** @} */ |
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200 | |
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201 | /** |
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202 | * @defgroup RTEMSScoreCPUV850CPUInterrupt Processor Dependent Interrupt Management |
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203 | * |
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204 | * @ingroup RTEMSScoreCPUV850 |
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205 | */ |
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206 | /** @{ **/ |
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207 | |
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208 | /** |
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209 | * Amount of extra stack (above minimum stack size) required by |
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210 | * MPCI receive server thread. Remember that in a multiprocessor |
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211 | * system this thread must exist and be able to process all directives. |
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212 | * |
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213 | * Port Specific Information: |
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214 | * |
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215 | * There is no reason to think the v850 needs extra MPCI receive |
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216 | * server stack. |
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217 | */ |
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218 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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219 | |
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220 | /** |
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221 | * This is defined if the port has a special way to report the ISR nesting |
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222 | * level. Most ports maintain the variable @a _ISR_Nest_level. |
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223 | */ |
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224 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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225 | |
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226 | /** @} */ |
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227 | |
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228 | /** |
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229 | * @addtogroup RTEMSScoreCPUV850CPUContext |
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230 | * Should be large enough to run all RTEMS tests. This ensures |
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231 | * that a "reasonable" small application should not have any problems. |
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232 | * |
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233 | * Port Specific Information: |
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234 | * |
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235 | * This should be very conservative on the v850. |
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236 | */ |
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237 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
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238 | |
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239 | #define CPU_SIZEOF_POINTER 4 |
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240 | |
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241 | /** |
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242 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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243 | * alignment does not take into account the requirements for the stack. |
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244 | * |
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245 | * Port Specific Information: |
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246 | * |
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247 | * There is no apparent reason why this should be larger than 8. |
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248 | */ |
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249 | #define CPU_ALIGNMENT 8 |
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250 | |
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251 | /** |
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252 | * This number corresponds to the byte alignment requirement for the |
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253 | * heap handler. This alignment requirement may be stricter than that |
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254 | * for the data types alignment specified by @ref CPU_ALIGNMENT. It is |
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255 | * common for the heap to follow the same alignment requirement as |
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256 | * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for |
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257 | * the heap, then this should be set to @ref CPU_ALIGNMENT. |
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258 | * |
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259 | * @note This does not have to be a power of 2 although it should be |
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260 | * a multiple of 2 greater than or equal to 2. The requirement |
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261 | * to be a multiple of 2 is because the heap uses the least |
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262 | * significant field of the front and back flags to indicate |
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263 | * that a block is in use or free. So you do not want any odd |
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264 | * length blocks really putting length data in that bit. |
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265 | * |
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266 | * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will |
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267 | * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that |
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268 | * elements allocated from the heap meet all restrictions. |
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269 | * |
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270 | * Port Specific Information: |
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271 | * |
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272 | * There is no apparent reason why this should be larger than CPU_ALIGNMENT. |
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273 | */ |
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274 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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275 | |
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276 | /** |
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277 | * The v850 has enough RAM where alignment to 16 may be desirable depending |
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278 | * on the cache properties. But this remains to be demonstrated. |
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279 | */ |
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280 | #define CPU_STACK_ALIGNMENT 8 |
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281 | |
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282 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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283 | |
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284 | /* |
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285 | * ISR handler macros |
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286 | */ |
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287 | |
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288 | /** |
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289 | * @addtogroup RTEMSScoreCPUV850CPUInterrupt |
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290 | */ |
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291 | /** @{ **/ |
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292 | |
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293 | /** |
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294 | * Disable all interrupts for an RTEMS critical section. The previous |
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295 | * level is returned in @a _isr_cookie. |
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296 | * |
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297 | * @param[out] _isr_cookie will contain the previous level cookie |
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298 | * |
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299 | * Port Specific Information: |
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300 | * |
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301 | * On the v850, we need to save the PSW and use "di" to disable interrupts. |
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302 | */ |
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303 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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304 | do { \ |
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305 | unsigned int _psw; \ |
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306 | \ |
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307 | v850_get_psw( _psw ); \ |
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308 | __asm__ __volatile__( "di" ); \ |
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309 | _isr_cookie = _psw; \ |
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310 | } while (0) |
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311 | |
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312 | /** |
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313 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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314 | * This indicates the end of an RTEMS critical section. The parameter |
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315 | * @a _isr_cookie is not modified. |
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316 | * |
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317 | * @param[in] _isr_cookie contain the previous level cookie |
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318 | * |
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319 | * Port Specific Information: |
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320 | * |
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321 | * On the v850, we simply need to restore the PSW. |
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322 | */ |
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323 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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324 | do { \ |
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325 | unsigned int _psw = (_isr_cookie); \ |
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326 | \ |
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327 | v850_set_psw( _psw ); \ |
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328 | } while (0) |
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329 | |
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330 | /** |
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331 | * This temporarily restores the interrupt to @a _isr_cookie before immediately |
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332 | * disabling them again. This is used to divide long RTEMS critical |
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333 | * sections into two or more parts. The parameter @a _isr_cookie is not |
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334 | * modified. |
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335 | * |
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336 | * @param[in] _isr_cookie contain the previous level cookie |
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337 | * |
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338 | * Port Specific Information: |
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339 | * |
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340 | * This saves at least one instruction over using enable/disable back to back. |
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341 | */ |
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342 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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343 | do { \ |
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344 | unsigned int _psw = (_isr_cookie); \ |
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345 | v850_set_psw( _psw ); \ |
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346 | __asm__ __volatile__( "di" ); \ |
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347 | } while (0) |
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348 | |
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349 | static inline bool _CPU_ISR_Is_enabled( uint32_t level ) |
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350 | { |
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351 | return ( level & V850_PSW_INTERRUPT_DISABLE_MASK ) |
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352 | != V850_PSW_INTERRUPT_DISABLE; |
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353 | } |
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354 | |
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355 | /** |
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356 | * This routine and @ref _CPU_ISR_Get_level |
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357 | * Map the interrupt level in task mode onto the hardware that the CPU |
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358 | * actually provides. Currently, interrupt levels which do not |
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359 | * map onto the CPU in a generic fashion are undefined. Someday, |
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360 | * it would be nice if these were "mapped" by the application |
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361 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
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362 | * 8 - 255 would be available for bsp/application specific meaning. |
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363 | * This could be used to manage a programmable interrupt controller |
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364 | * via the rtems_task_mode directive. |
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365 | * |
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366 | * Port Specific Information: |
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367 | * |
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368 | * On the v850, level 0 is enabled. Non-zero is disabled. |
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369 | */ |
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370 | #define _CPU_ISR_Set_level( new_level ) \ |
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371 | do { \ |
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372 | if ( new_level ) \ |
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373 | __asm__ __volatile__( "di" ); \ |
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374 | else \ |
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375 | __asm__ __volatile__( "ei" ); \ |
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376 | } while (0) |
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377 | |
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378 | /** |
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379 | * Return the current interrupt disable level for this task in |
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380 | * the format used by the interrupt level portion of the task mode. |
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381 | * |
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382 | * @note This routine usually must be implemented as a subroutine. |
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383 | * |
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384 | * Port Specific Information: |
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385 | * |
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386 | * This method is implemented in C on the v850. |
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387 | */ |
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388 | uint32_t _CPU_ISR_Get_level( void ); |
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389 | |
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390 | /* end of ISR handler macros */ |
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391 | |
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392 | /** @} */ |
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393 | |
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394 | /* Context handler macros */ |
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395 | |
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396 | /** |
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397 | * @addtogroup RTEMSScoreCPUV850CPUContext |
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398 | * Initialize the context to a state suitable for starting a |
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399 | * task after a context restore operation. Generally, this |
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400 | * involves: |
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401 | * |
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402 | * - setting a starting address |
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403 | * - preparing the stack |
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404 | * - preparing the stack and frame pointers |
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405 | * - setting the proper interrupt level in the context |
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406 | * - initializing the floating point context |
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407 | * |
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408 | * This routine generally does not set any unnecessary register |
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409 | * in the context. The state of the "general data" registers is |
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410 | * undefined at task start time. |
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411 | * |
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412 | * @param[in] _the_context is the context structure to be initialized |
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413 | * @param[in] _stack_base is the lowest physical address of this task's stack |
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414 | * @param[in] _size is the size of this task's stack |
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415 | * @param[in] _isr is the interrupt disable level |
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416 | * @param[in] _entry_point is the thread's entry point. This is |
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417 | * always @a _Thread_Handler |
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418 | * @param[in] _is_fp is TRUE if the thread is to be a floating |
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419 | * point thread. This is typically only used on CPUs where the |
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420 | * FPU may be easily disabled by software such as on the SPARC |
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421 | * where the PSR contains an enable FPU bit. |
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422 | * @param[in] tls_area is the thread-local storage (TLS) area |
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423 | * |
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424 | * Port Specific Information: |
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425 | * |
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426 | * This method is implemented in C on the v850. |
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427 | */ |
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428 | void _CPU_Context_Initialize( |
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429 | Context_Control *the_context, |
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430 | uint32_t *stack_base, |
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431 | uint32_t size, |
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432 | uint32_t new_level, |
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433 | void *entry_point, |
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434 | bool is_fp, |
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435 | void *tls_area |
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436 | ); |
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437 | |
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438 | /** |
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439 | * This routine is responsible for somehow restarting the currently |
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440 | * executing task. If you are lucky, then all that is necessary |
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441 | * is restoring the context. Otherwise, there will need to be |
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442 | * a special assembly routine which does something special in this |
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443 | * case. For many ports, simply adding a label to the restore path |
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444 | * of @ref _CPU_Context_switch will work. On other ports, it may be |
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445 | * possibly to load a few arguments and jump to the restore path. It will |
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446 | * not work if restarting self conflicts with the stack frame |
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447 | * assumptions of restoring a context. |
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448 | * |
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449 | * Port Specific Information: |
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450 | * |
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451 | * On the v850, we require a special entry point to restart a task. |
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452 | */ |
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453 | #define _CPU_Context_Restart_self( _the_context ) \ |
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454 | _CPU_Context_restore( (_the_context) ); |
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455 | |
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456 | /* XXX this should be possible to remove */ |
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457 | #if 0 |
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458 | /** |
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459 | * This routine initializes the FP context area passed to it to. |
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460 | * There are a few standard ways in which to initialize the |
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461 | * floating point context. The code included for this macro assumes |
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462 | * that this is a CPU in which a "initial" FP context was saved into |
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463 | * @a _CPU_Null_fp_context and it simply copies it to the destination |
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464 | * context passed to it. |
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465 | * |
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466 | * Other floating point context save/restore models include: |
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467 | * -# not doing anything, and |
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468 | * -# putting a "null FP status word" in the correct place in the FP context. |
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469 | * |
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470 | * @param[in] _destination is the floating point context area |
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471 | * |
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472 | * Port Specific Information: |
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473 | * |
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474 | * XXX document implementation including references if appropriate |
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475 | */ |
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476 | #define _CPU_Context_Initialize_fp( _destination ) \ |
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477 | { \ |
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478 | } |
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479 | #endif |
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480 | |
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481 | /* end of Context handler macros */ |
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482 | |
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483 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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484 | |
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485 | #define CPU_USE_LIBC_INIT_FINI_ARRAY FALSE |
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486 | |
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487 | /* functions */ |
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488 | |
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489 | /** |
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490 | * @brief CPU initialize. |
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491 | * This routine performs CPU dependent initialization. |
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492 | * |
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493 | * Port Specific Information: |
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494 | * |
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495 | * This is implemented in C. |
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496 | * |
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497 | * v850 CPU Dependent Source |
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498 | */ |
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499 | void _CPU_Initialize(void); |
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500 | |
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501 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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502 | |
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503 | /** |
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504 | * @addtogroup RTEMSScoreCPUV850CPUContext |
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505 | */ |
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506 | /**@{**/ |
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507 | |
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508 | /** |
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509 | * This routine switches from the run context to the heir context. |
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510 | * |
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511 | * @param[in] run points to the context of the currently executing task |
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512 | * @param[in] heir points to the context of the heir task |
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513 | * |
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514 | * Port Specific Information: |
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515 | * |
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516 | * This is implemented in assembly on the v850. |
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517 | */ |
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518 | void _CPU_Context_switch( |
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519 | Context_Control *run, |
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520 | Context_Control *heir |
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521 | ); |
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522 | |
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523 | /** |
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524 | * This routine is generally used only to restart self in an |
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525 | * efficient manner. It may simply be a label in @ref _CPU_Context_switch. |
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526 | * |
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527 | * @param[in] new_context points to the context to be restored. |
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528 | * |
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529 | * @note May be unnecessary to reload some registers. |
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530 | * |
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531 | * Port Specific Information: |
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532 | * |
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533 | * This is implemented in assembly on the v850. |
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534 | */ |
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535 | RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); |
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536 | |
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537 | /* XXX this should be possible to remove */ |
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538 | #if 0 |
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539 | /** |
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540 | * This routine saves the floating point context passed to it. |
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541 | * |
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542 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
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543 | * point context area |
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544 | * |
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545 | * @return on output @a *fp_context_ptr will contain the address that |
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546 | * should be used with @ref _CPU_Context_restore_fp to restore this context. |
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547 | * |
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548 | * Port Specific Information: |
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549 | * |
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550 | * XXX document implementation including references if appropriate |
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551 | */ |
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552 | void _CPU_Context_save_fp( |
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553 | Context_Control_fp **fp_context_ptr |
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554 | ); |
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555 | #endif |
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556 | |
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557 | /* XXX this should be possible to remove */ |
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558 | #if 0 |
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559 | /** |
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560 | * This routine restores the floating point context passed to it. |
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561 | * |
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562 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
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563 | * point context area to restore |
---|
564 | * |
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565 | * @return on output @a *fp_context_ptr will contain the address that |
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566 | * should be used with @ref _CPU_Context_save_fp to save this context. |
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567 | * |
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568 | * Port Specific Information: |
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569 | * |
---|
570 | * XXX document implementation including references if appropriate |
---|
571 | */ |
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572 | void _CPU_Context_restore_fp( |
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573 | Context_Control_fp **fp_context_ptr |
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574 | ); |
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575 | #endif |
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576 | |
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577 | /** @} */ |
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578 | |
---|
579 | /* FIXME */ |
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580 | typedef CPU_Interrupt_frame CPU_Exception_frame; |
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581 | |
---|
582 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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583 | |
---|
584 | /** |
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585 | * @defgroup RTEMSScoreCPUV850CPUEndian CPUEndian |
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586 | * |
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587 | * @ingroup RTEMSScoreCPUV850 |
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588 | * |
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589 | * @brief CPUEndian |
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590 | */ |
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591 | /** @{ */ |
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592 | |
---|
593 | /** |
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594 | * The following routine swaps the endian format of an unsigned int. |
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595 | * It must be static because it is referenced indirectly. |
---|
596 | * |
---|
597 | * This version will work on any processor, but if there is a better |
---|
598 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
599 | * |
---|
600 | * swap least significant two bytes with 16-bit rotate |
---|
601 | * swap upper and lower 16-bits |
---|
602 | * swap most significant two bytes with 16-bit rotate |
---|
603 | * |
---|
604 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
605 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
606 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
607 | * that interrupts would probably have to be disabled to ensure that |
---|
608 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
609 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
610 | * endianness for ALL fetches -- both code and data -- so the code |
---|
611 | * will be fetched incorrectly. |
---|
612 | * |
---|
613 | * @param[in] value is the value to be swapped |
---|
614 | * @return the value after being endian swapped |
---|
615 | * |
---|
616 | * Port Specific Information: |
---|
617 | * |
---|
618 | * The v850 has a single instruction to swap endianness on a 32 bit quantity. |
---|
619 | */ |
---|
620 | static inline uint32_t CPU_swap_u32( |
---|
621 | uint32_t value |
---|
622 | ) |
---|
623 | { |
---|
624 | unsigned int swapped; |
---|
625 | |
---|
626 | #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) |
---|
627 | unsigned int v; |
---|
628 | |
---|
629 | v = value; |
---|
630 | __asm__ __volatile__ ("bsw %0, %1" : "=r" (v), "=&r" (swapped) ); |
---|
631 | #else |
---|
632 | uint32_t byte1, byte2, byte3, byte4; |
---|
633 | |
---|
634 | byte4 = (value >> 24) & 0xff; |
---|
635 | byte3 = (value >> 16) & 0xff; |
---|
636 | byte2 = (value >> 8) & 0xff; |
---|
637 | byte1 = value & 0xff; |
---|
638 | |
---|
639 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
640 | #endif |
---|
641 | return swapped; |
---|
642 | } |
---|
643 | |
---|
644 | /** |
---|
645 | * This routine swaps a 16 bir quantity. |
---|
646 | * |
---|
647 | * @param[in] value is the value to be swapped |
---|
648 | * @return the value after being endian swapped |
---|
649 | * |
---|
650 | * Port Specific Information: |
---|
651 | * |
---|
652 | * The v850 has a single instruction to swap endianness on a 16 bit quantity. |
---|
653 | */ |
---|
654 | static inline uint16_t CPU_swap_u16( uint16_t value ) |
---|
655 | { |
---|
656 | unsigned int swapped; |
---|
657 | |
---|
658 | #if (V850_HAS_BYTE_SWAP_INSTRUCTION == 1) |
---|
659 | unsigned int v; |
---|
660 | |
---|
661 | v = value; |
---|
662 | __asm__ __volatile__ ("bsh %0, %1" : "=r" (v), "=&r" (swapped) ); |
---|
663 | #else |
---|
664 | swapped = ((value & 0xff) << 8) | ((value >> 8) & 0xff); |
---|
665 | #endif |
---|
666 | return swapped; |
---|
667 | } |
---|
668 | |
---|
669 | /** @} */ |
---|
670 | |
---|
671 | typedef uint32_t CPU_Counter_ticks; |
---|
672 | |
---|
673 | uint32_t _CPU_Counter_frequency( void ); |
---|
674 | |
---|
675 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
676 | |
---|
677 | /** Type that can store a 32-bit integer or a pointer. */ |
---|
678 | typedef uintptr_t CPU_Uint32ptr; |
---|
679 | |
---|
680 | #ifdef __cplusplus |
---|
681 | } |
---|
682 | #endif |
---|
683 | |
---|
684 | #endif |
---|