source: rtems/cpukit/score/cpu/v850/cpu.c @ 2d7ae960

4.115
Last change on this file since 2d7ae960 was 2d7ae960, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 11, 2012 at 6:37:29 PM

v850 port: Initial addition with BSP for simulator in GDB

Port

+ v850 does not have appear to have any optimized bit scan instructions
+ v850 does have single instructions for wap u16 and u32
+ Code path optimization preferences set
+ Add BSP variants for each GCC CPU model flag and a README

  • v850e1 variant does not work (fails during BSP initialization)

BSP for GDB v850 Simulator

+ linkcmds matches defaults in GDB simulator with RTEMS mods
+ crt1.c added from v850 newlib port for main()
+ BSP exits cleanly
+ printk and console I/O work
+ uses clock tick from IDLE task
+ Tests not requiring real clock ISR work

Documentation

+ CPU Supplment chapter for v850 added

  • Property mode set to 100644
File size: 2.3 KB
Line 
1/**
2 *  @file
3 *
4 *  v850 CPU Dependent Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2012.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 */
15
16#ifdef HAVE_CONFIG_H
17#include "config.h"
18#endif
19
20#include <rtems/system.h>
21#include <rtems/score/isr.h>
22#include <rtems/score/wkspace.h>
23
24#include <string.h> /* for memset */
25
26/*
27 *  v850 Specific Information:
28 *
29 *  So far nothing known to be needed at this point during initialization.
30 */
31void _CPU_Initialize(void)
32{
33}
34
35/*
36 *  v850 Specific Information:
37 *
38 *  This method returns 0 if interrupts are enabled and 1 if they are disabled.
39 *  The v850 only has two interrupt levels (on and off).
40 */
41uint32_t _CPU_ISR_Get_level( void )
42{
43  unsigned int psw;
44
45  v850_get_psw( psw );
46
47  if ( (psw & V850_PSW_INTERRUPT_DISABLE_MASK) == V850_PSW_INTERRUPT_DISABLE )
48    return 1;
49
50  return 0;
51}
52
53/*
54 *  v850 Specific Information:
55 *
56 *  This method initializes a v850 context control structure.
57 */
58void _CPU_Context_Initialize(
59  Context_Control  *the_context,
60  uint32_t         *stack_base,
61  uint32_t          size,
62  uint32_t          new_level,
63  void             *entry_point,
64  bool              is_fp
65)
66{
67  uint32_t  stack_high;  /* highest "stack aligned" address */
68  uint32_t  psw;         /* highest "stack aligned" address */
69
70  memset( the_context, 0, sizeof(Context_Control) );
71
72  /*
73   *  On CPUs with stacks which grow down, we build the stack
74   *  based on the stack_high address.
75   */
76  stack_high = ((uint32_t)(stack_base) + size);
77  stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
78
79  v850_get_psw( psw );
80  psw &= ~V850_PSW_INTERRUPT_DISABLE_MASK;
81  if ( new_level )
82    psw |= V850_PSW_INTERRUPT_DISABLE;
83  else
84    psw |= V850_PSW_INTERRUPT_ENABLE;
85
86  the_context->r31              = (uint32_t) entry_point;
87  the_context->r3_stack_pointer = stack_high;
88  the_context->psw              = psw;
89
90#if 0
91  printk( "the_context = %p\n",      the_context );
92  printk( "stack base  = 0x%08x\n",  stack_base );
93  printk( "stack size  = 0x%08x\n",  size );
94  printk( "sp          = 0x%08x\n",  the_context->r3_stack_pointer );
95  printk( "psw         = 0x%08x\n",  the_context->psw );
96#endif
97}
98
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