source: rtems/cpukit/score/cpu/unix/rtems/score/cpu.h @ ee29de05

4.104.114.95
Last change on this file since ee29de05 was ee29de05, checked in by Joel Sherrill <joel.sherrill@…>, on 12/04/07 at 22:19:10

2007-12-04 Joel Sherrill <joel.sherrill@…>

  • cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU Table to Configuration Table. Eliminate CPU Table from all ports. Delete references to CPU Table in all forms.
  • Property mode set to 100644
File size: 31.1 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the
7 *  UNIX port of RTEMS.
8 *
9 *  COPYRIGHT (c) 1994 by Division Incorporated
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 *
15 *  COPYRIGHT (c) 1989-2006.
16 *  On-Line Applications Research Corporation (OAR).
17 *
18 *  The license and distribution terms for this file may in
19 *  the file LICENSE in this distribution or at
20 *  http://www.rtems.com/license/LICENSE.
21 *
22 *  $Id$
23 */
24
25#ifndef _RTEMS_SCORE_CPU_H
26#define _RTEMS_SCORE_CPU_H
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32#include <rtems/score/unix.h>              /* pick up machine definitions */
33#ifndef ASM
34#include <rtems/score/types.h>
35#endif
36
37#if defined(linux)
38#define MALLOC_0_RETURNS_NULL
39#endif
40
41/* conditional compilation parameters */
42
43/*
44 *  Should the calls to _Thread_Enable_dispatch be inlined?
45 *
46 *  If TRUE, then they are inlined.
47 *  If FALSE, then a subroutine call is made.
48 *
49 *  Basically this is an example of the classic trade-off of size
50 *  versus speed.  Inlining the call (TRUE) typically increases the
51 *  size of RTEMS while speeding up the enabling of dispatching.
52 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
53 *  only be 0 or 1 unless you are in an interrupt handler and that
54 *  interrupt handler invokes the executive.]  When not inlined
55 *  something calls _Thread_Enable_dispatch which in turns calls
56 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
57 *  one subroutine call is avoided entirely.]
58 */
59
60#define CPU_INLINE_ENABLE_DISPATCH       FALSE
61
62/*
63 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
64 *  be unrolled one time?  In unrolled each iteration of the loop examines
65 *  two "nodes" on the chain being searched.  Otherwise, only one node
66 *  is examined per iteration.
67 *
68 *  If TRUE, then the loops are unrolled.
69 *  If FALSE, then the loops are not unrolled.
70 *
71 *  The primary factor in making this decision is the cost of disabling
72 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
73 *  body of the loop.  On some CPUs, the flash is more expensive than
74 *  one iteration of the loop body.  In this case, it might be desirable
75 *  to unroll the loop.  It is important to note that on some CPUs, this
76 *  code is the longest interrupt disable period in RTEMS.  So it is
77 *  necessary to strike a balance when setting this parameter.
78 */
79
80#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
81
82/*
83 *  Does RTEMS manage a dedicated interrupt stack in software?
84 *
85 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
86 *  If FALSE, nothing is done.
87 *
88 *  If the CPU supports a dedicated interrupt stack in hardware,
89 *  then it is generally the responsibility of the BSP to allocate it
90 *  and set it up.
91 *
92 *  If the CPU does not support a dedicated interrupt stack, then
93 *  the porter has two options: (1) execute interrupts on the
94 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
95 *  interrupt stack.
96 *
97 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
98 *
99 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
100 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
101 *  possible that both are FALSE for a particular CPU.  Although it
102 *  is unclear what that would imply about the interrupt processing
103 *  procedure on that CPU.
104 */
105
106#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
107
108/*
109 *  Does this CPU have hardware support for a dedicated interrupt stack?
110 *
111 *  If TRUE, then it must be installed during initialization.
112 *  If FALSE, then no installation is performed.
113 *
114 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
115 *
116 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
117 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
118 *  possible that both are FALSE for a particular CPU.  Although it
119 *  is unclear what that would imply about the interrupt processing
120 *  procedure on that CPU.
121 */
122
123#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
124
125/*
126 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
127 *
128 *  If TRUE, then the memory is allocated during initialization.
129 *  If FALSE, then the memory is allocated during initialization.
130 *
131 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
132 */
133
134#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
135
136/*
137 *  Does the RTEMS invoke the user's ISR with the vector number and
138 *  a pointer to the saved interrupt frame (1) or just the vector
139 *  number (0)?
140 */
141
142#define CPU_ISR_PASSES_FRAME_POINTER 0
143
144/*
145 *  Does the CPU have hardware floating point?
146 *
147 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
148 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
149 *
150 *  If there is a FP coprocessor such as the i387 or mc68881, then
151 *  the answer is TRUE.
152 *
153 *  The macro name "UNIX_HAS_FPU" should be made CPU specific.
154 *  It indicates whether or not this CPU model has FP support.  For
155 *  example, it would be possible to have an i386_nofp CPU model
156 *  which set this to false to indicate that you have an i386 without
157 *  an i387 and wish to leave floating point support out of RTEMS.
158 */
159
160#define CPU_HARDWARE_FP     TRUE
161#define CPU_SOFTWARE_FP     FALSE
162
163/*
164 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
165 *
166 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
167 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
168 *
169 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
170 */
171
172#define CPU_ALL_TASKS_ARE_FP     FALSE
173
174/*
175 *  Should the IDLE task have a floating point context?
176 *
177 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
178 *  and it has a floating point context which is switched in and out.
179 *  If FALSE, then the IDLE task does not have a floating point context.
180 *
181 *  Setting this to TRUE negatively impacts the time required to preempt
182 *  the IDLE task from an interrupt because the floating point context
183 *  must be saved as part of the preemption.
184 */
185
186#define CPU_IDLE_TASK_IS_FP      FALSE
187
188/*
189 *  Should the saving of the floating point registers be deferred
190 *  until a context switch is made to another different floating point
191 *  task?
192 *
193 *  If TRUE, then the floating point context will not be stored until
194 *  necessary.  It will remain in the floating point registers and not
195 *  disturned until another floating point task is switched to.
196 *
197 *  If FALSE, then the floating point context is saved when a floating
198 *  point task is switched out and restored when the next floating point
199 *  task is restored.  The state of the floating point registers between
200 *  those two operations is not specified.
201 *
202 *  If the floating point context does NOT have to be saved as part of
203 *  interrupt dispatching, then it should be safe to set this to TRUE.
204 *
205 *  Setting this flag to TRUE results in using a different algorithm
206 *  for deciding when to save and restore the floating point context.
207 *  The deferred FP switch algorithm minimizes the number of times
208 *  the FP context is saved and restored.  The FP context is not saved
209 *  until a context switch is made to another, different FP task.
210 *  Thus in a system with only one FP task, the FP context will never
211 *  be saved or restored.
212 */
213
214#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
215
216/*
217 *  Does this port provide a CPU dependent IDLE task implementation?
218 *
219 *  If TRUE, then the routine _CPU_Thread_Idle_body
220 *  must be provided and is the default IDLE thread body instead of
221 *  _CPU_Thread_Idle_body.
222 *
223 *  If FALSE, then use the generic IDLE thread body if the BSP does
224 *  not provide one.
225 *
226 *  This is intended to allow for supporting processors which have
227 *  a low power or idle mode.  When the IDLE thread is executed, then
228 *  the CPU can be powered down.
229 *
230 *  The order of precedence for selecting the IDLE thread body is:
231 *
232 *    1.  BSP provided
233 *    2.  CPU dependent (if provided)
234 *    3.  generic (if no BSP and no CPU dependent)
235 */
236
237#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
238
239/*
240 *  Does the stack grow up (toward higher addresses) or down
241 *  (toward lower addresses)?
242 *
243 *  If TRUE, then the grows upward.
244 *  If FALSE, then the grows toward smaller addresses.
245 */
246
247#if defined(__hppa__)
248#define CPU_STACK_GROWS_UP               TRUE
249#elif defined(__sparc__) || defined(__i386__)
250#define CPU_STACK_GROWS_UP               FALSE
251#else
252#error "unknown CPU!!"
253#endif
254
255
256/*
257 *  The following is the variable attribute used to force alignment
258 *  of critical RTEMS structures.  On some processors it may make
259 *  sense to have these aligned on tighter boundaries than
260 *  the minimum requirements of the compiler in order to have as
261 *  much of the critical data area as possible in a cache line.
262 *
263 *  The placement of this macro in the declaration of the variables
264 *  is based on the syntactically requirements of the GNU C
265 *  "__attribute__" extension.  For example with GNU C, use
266 *  the following to force a structures to a 32 byte boundary.
267 *
268 *      __attribute__ ((aligned (32)))
269 *
270 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
271 *         To benefit from using this, the data must be heavily
272 *         used so it will stay in the cache and used frequently enough
273 *         in the executive to justify turning this on.
274 *
275 *  This is really not critical on the POSIX simulator ports as
276 *  performance is not the goal here.
277 */
278
279#define CPU_STRUCTURE_ALIGNMENT
280
281/*
282 *  Define what is required to specify how the network to host conversion
283 *  routines are handled.
284 */
285
286#if defined(__hppa__) || defined(__sparc__)
287#define CPU_BIG_ENDIAN                           TRUE
288#define CPU_LITTLE_ENDIAN                        FALSE
289#elif defined(__i386__)
290#define CPU_BIG_ENDIAN                           FALSE
291#define CPU_LITTLE_ENDIAN                        TRUE
292#else
293#error "Unknown CPU!!!"
294#endif
295
296/*
297 *  The following defines the number of bits actually used in the
298 *  interrupt field of the task mode.  How those bits map to the
299 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
300 */
301
302#define CPU_MODES_INTERRUPT_MASK   0x00000001
303
304#define CPU_NAME "UNIX"
305
306/*
307 *  Processor defined structures required for cpukit/score.
308 */
309
310/* may need to put some structures here.  */
311
312#if defined(__hppa__)
313/*
314 * Word indices within a jmp_buf structure
315 */
316
317#ifdef RTEMS_NEWLIB_SETJMP
318#define RP_OFF       6
319#define SP_OFF       2
320#define R3_OFF      10
321#define R4_OFF      11
322#define R5_OFF      12
323#define R6_OFF      13
324#define R7_OFF      14
325#define R8_OFF      15
326#define R9_OFF      16
327#define R10_OFF     17
328#define R11_OFF     18
329#define R12_OFF     19
330#define R13_OFF     20
331#define R14_OFF     21
332#define R15_OFF     22
333#define R16_OFF     23
334#define R17_OFF     24
335#define R18_OFF     25
336#define DP_OFF      26
337#endif
338
339#ifdef RTEMS_UNIXLIB_SETJMP
340#define RP_OFF       0
341#define SP_OFF       1
342#define R3_OFF       4
343#define R4_OFF       5
344#define R5_OFF       6
345#define R6_OFF       7
346#define R7_OFF       8
347#define R8_OFF       9
348#define R9_OFF      10
349#define R10_OFF     11
350#define R11_OFF     12
351#define R12_OFF     13
352#define R13_OFF     14
353#define R14_OFF     15
354#define R15_OFF     16
355#define R16_OFF     17
356#define R17_OFF     18
357#define R18_OFF     19
358#define DP_OFF      20
359#endif
360#endif
361
362#if defined(__i386__)
363 
364#ifdef RTEMS_NEWLIB
365#error "Newlib not installed"
366#endif
367 
368/*
369 *  For i386 targets
370 */
371 
372#ifdef RTEMS_UNIXLIB
373#if defined(__FreeBSD__)
374#define RET_OFF    0
375#define EBX_OFF    1
376#define EBP_OFF    2
377#define ESP_OFF    3
378#define ESI_OFF    4
379#define EDI_OFF    5
380#elif defined(__CYGWIN__)
381#define EAX_OFF    0
382#define EBX_OFF    1
383#define ECX_OFF    2
384#define EDX_OFF    3
385#define ESI_OFF    4
386#define EDI_OFF    5
387#define EBP_OFF    6
388#define ESP_OFF    7
389#define RET_OFF    8
390#else
391/* Linux */
392#define EBX_OFF    0
393#define ESI_OFF    1
394#define EDI_OFF    2
395#define EBP_OFF    3
396#define ESP_OFF    4
397#define RET_OFF    5
398#endif
399#endif
400 
401#endif
402 
403#if defined(__sparc__)
404
405/*
406 *  Word indices within a jmp_buf structure
407 */
408 
409#ifdef RTEMS_NEWLIB
410#define ADDR_ADJ_OFFSET -8
411#define SP_OFF    0
412#define RP_OFF    1
413#define FP_OFF    2
414#endif
415
416#ifdef RTEMS_UNIXLIB
417#define ADDR_ADJ_OFFSET 0
418#define G0_OFF    0
419#define SP_OFF    1
420#define RP_OFF    2   
421#define FP_OFF    3
422#define I7_OFF    4
423#endif
424
425#endif
426
427/*
428 * Contexts
429 *
430 *  Generally there are 2 types of context to save.
431 *     1. Interrupt registers to save
432 *     2. Task level registers to save
433 *
434 *  This means we have the following 3 context items:
435 *     1. task level context stuff::  Context_Control
436 *     2. floating point task stuff:: Context_Control_fp
437 *     3. special interrupt level context :: Context_Control_interrupt
438 *
439 *  On some processors, it is cost-effective to save only the callee
440 *  preserved registers during a task context switch.  This means
441 *  that the ISR code needs to save those registers which do not
442 *  persist across function calls.  It is not mandatory to make this
443 *  distinctions between the caller/callee saves registers for the
444 *  purpose of minimizing context saved during task switch and on interrupts.
445 *  If the cost of saving extra registers is minimal, simplicity is the
446 *  choice.  Save the same context on interrupt entry as for tasks in
447 *  this case.
448 *
449 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
450 *  care should be used in designing the context area.
451 *
452 *  On some CPUs with hardware floating point support, the Context_Control_fp
453 *  structure will not be used or it simply consist of an array of a
454 *  fixed number of bytes.   This is done when the floating point context
455 *  is dumped by a "FP save context" type instruction and the format
456 *  is not really defined by the CPU.  In this case, there is no need
457 *  to figure out the exact format -- only the size.  Of course, although
458 *  this is enough information for RTEMS, it is probably not enough for
459 *  a debugger such as gdb.  But that is another problem.
460 */
461
462/*
463 *  This is really just the area for the following fields.
464 *
465 *    jmp_buf    regs;
466 *    uint32_t   isr_level;
467 *
468 *  Doing it this way avoids conflicts between the native stuff and the
469 *  RTEMS stuff.
470 *
471 *  NOTE:
472 *      hpux9 setjmp is optimized for the case where the setjmp buffer
473 *      is 8 byte aligned.  In a RISC world, this seems likely to enable
474 *      8 byte copies, especially for the float registers.
475 *      So we always align them on 8 byte boundaries.
476 */
477
478#ifdef __GNUC__
479#define CONTEXT_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (8)))
480#else
481#define CONTEXT_STRUCTURE_ALIGNMENT
482#endif
483
484typedef struct {
485  char      Area[ SIZEOF_CPU_CONTEXT ] CONTEXT_STRUCTURE_ALIGNMENT;
486} Context_Control;
487
488typedef struct {
489} Context_Control_fp;
490
491typedef struct {
492} CPU_Interrupt_frame;
493
494/*
495 *  This variable is optional.  It is used on CPUs on which it is difficult
496 *  to generate an "uninitialized" FP context.  It is filled in by
497 *  _CPU_Initialize and copied into the task's FP context area during
498 *  _CPU_Context_Initialize.
499 */
500
501SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
502
503/*
504 *  On some CPUs, RTEMS supports a software managed interrupt stack.
505 *  This stack is allocated by the Interrupt Manager and the switch
506 *  is performed in _ISR_Handler.  These variables contain pointers
507 *  to the lowest and highest addresses in the chunk of memory allocated
508 *  for the interrupt stack.  Since it is unknown whether the stack
509 *  grows up or down (in general), this give the CPU dependent
510 *  code the option of picking the version it wants to use.
511 *
512 *  NOTE: These two variables are required if the macro
513 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
514 */
515
516SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
517SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
518
519/*
520 *  With some compilation systems, it is difficult if not impossible to
521 *  call a high-level language routine from assembly language.  This
522 *  is especially true of commercial Ada compilers and name mangling
523 *  C++ ones.  This variable can be optionally defined by the CPU porter
524 *  and contains the address of the routine _Thread_Dispatch.  This
525 *  can make it easier to invoke that routine at the end of the interrupt
526 *  sequence (if a dispatch is necessary).
527 */
528
529SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
530
531/*
532 *  Nothing prevents the porter from declaring more CPU specific variables.
533 */
534
535/* XXX: if needed, put more variables here */
536
537/*
538 *  The size of the floating point context area.  On some CPUs this
539 *  will not be a "sizeof" because the format of the floating point
540 *  area is not defined -- only the size is.  This is usually on
541 *  CPUs with a "floating point save context" instruction.
542 */
543
544#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
545
546/*
547 * The size of a frame on the stack
548 */
549
550#if defined(__hppa__)
551#define CPU_FRAME_SIZE  (32 * 4)
552#elif defined(__sparc__)
553#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
554#elif defined(__i386__)
555#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
556#else
557#error "Unknown CPU!!!"
558#endif
559
560/*
561 *  Amount of extra stack (above minimum stack size) required by
562 *  MPCI receive server thread.  Remember that in a multiprocessor
563 *  system this thread must exist and be able to process all directives.
564 */
565
566#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
567
568/*
569 *  This defines the number of entries in the ISR_Vector_table managed
570 *  by RTEMS.
571 */
572
573#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
574#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
575
576/*
577 *  This is defined if the port has a special way to report the ISR nesting
578 *  level.  Most ports maintain the variable _ISR_Nest_level.
579 */
580
581#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
582
583/*
584 *  Should be large enough to run all RTEMS tests.  This ensures
585 *  that a "reasonable" small application should not have any problems.
586 */
587
588#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
589
590/*
591 *  CPU's worst alignment requirement for data types on a byte boundary.  This
592 *  alignment does not take into account the requirements for the stack.
593 */
594
595#define CPU_ALIGNMENT              8
596
597/*
598 *  This number corresponds to the byte alignment requirement for the
599 *  heap handler.  This alignment requirement may be stricter than that
600 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
601 *  common for the heap to follow the same alignment requirement as
602 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
603 *  then this should be set to CPU_ALIGNMENT.
604 *
605 *  NOTE:  This does not have to be a power of 2.  It does have to
606 *         be greater or equal to than CPU_ALIGNMENT.
607 */
608
609#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
610
611/*
612 *  This number corresponds to the byte alignment requirement for memory
613 *  buffers allocated by the partition manager.  This alignment requirement
614 *  may be stricter than that for the data types alignment specified by
615 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
616 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
617 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
618 *
619 *  NOTE:  This does not have to be a power of 2.  It does have to
620 *         be greater or equal to than CPU_ALIGNMENT.
621 */
622
623#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
624
625/*
626 *  This number corresponds to the byte alignment requirement for the
627 *  stack.  This alignment requirement may be stricter than that for the
628 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
629 *  is strict enough for the stack, then this should be set to 0.
630 *
631 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
632 */
633
634#define CPU_STACK_ALIGNMENT        64
635
636/*
637 *  ISR handler macros
638 */
639
640/*
641 *  Support routine to initialize the RTEMS vector table after it is allocated.
642 */
643
644void _CPU_Initialize_vectors(void);
645
646/*
647 *  Disable all interrupts for an RTEMS critical section.  The previous
648 *  level is returned in _level.
649 */
650
651extern uint32_t   _CPU_ISR_Disable_support(void);
652
653#define _CPU_ISR_Disable( _level ) \
654    do { \
655      (_level) = _CPU_ISR_Disable_support(); \
656    } while ( 0 )
657
658/*
659 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
660 *  This indicates the end of an RTEMS critical section.  The parameter
661 *  _level is not modified.
662 */
663
664void _CPU_ISR_Enable(uint32_t   level);
665
666/*
667 *  This temporarily restores the interrupt to _level before immediately
668 *  disabling them again.  This is used to divide long RTEMS critical
669 *  sections into two or more parts.  The parameter _level is not
670 * modified.
671 */
672
673#define _CPU_ISR_Flash( _level ) \
674  do { \
675      register uint32_t   _ignored = 0; \
676      _CPU_ISR_Enable( (_level) ); \
677      _CPU_ISR_Disable( _ignored ); \
678  } while ( 0 )
679
680/*
681 *  Map interrupt level in task mode onto the hardware that the CPU
682 *  actually provides.  Currently, interrupt levels which do not
683 *  map onto the CPU in a generic fashion are undefined.  Someday,
684 *  it would be nice if these were "mapped" by the application
685 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
686 *  8 - 255 would be available for bsp/application specific meaning.
687 *  This could be used to manage a programmable interrupt controller
688 *  via the rtems_task_mode directive.
689 */
690
691#define _CPU_ISR_Set_level( new_level ) \
692  { \
693    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
694    else                  _CPU_ISR_Enable( 1 ); \
695  }
696
697uint32_t   _CPU_ISR_Get_level( void );
698
699/* end of ISR handler macros */
700
701/* Context handler macros */
702
703/*
704 *  This routine is responsible for somehow restarting the currently
705 *  executing task.  If you are lucky, then all that is necessary
706 *  is restoring the context.  Otherwise, there will need to be
707 *  a special assembly routine which does something special in this
708 *  case.  Context_Restore should work most of the time.  It will
709 *  not work if restarting self conflicts with the stack frame
710 *  assumptions of restoring a context.
711 */
712
713#define _CPU_Context_Restart_self( _the_context ) \
714   _CPU_Context_restore( (_the_context) );
715
716/*
717 *  The purpose of this macro is to allow the initial pointer into
718 *  a floating point context area (used to save the floating point
719 *  context) to be at an arbitrary place in the floating point
720 *  context area.
721 *
722 *  This is necessary because some FP units are designed to have
723 *  their context saved as a stack which grows into lower addresses.
724 *  Other FP units can be saved by simply moving registers into offsets
725 *  from the base of the context area.  Finally some FP units provide
726 *  a "dump context" instruction which could fill in from high to low
727 *  or low to high based on the whim of the CPU designers.
728 */
729
730#define _CPU_Context_Fp_start( _base, _offset ) \
731   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
732
733/*
734 *  This routine initializes the FP context area passed to it to.
735 *  There are a few standard ways in which to initialize the
736 *  floating point context.  The code included for this macro assumes
737 *  that this is a CPU in which a "initial" FP context was saved into
738 *  _CPU_Null_fp_context and it simply copies it to the destination
739 *  context passed to it.
740 *
741 *  Other models include (1) not doing anything, and (2) putting
742 *  a "null FP status word" in the correct place in the FP context.
743 */
744
745#define _CPU_Context_Initialize_fp( _destination ) \
746  { \
747   *(*(_destination)) = _CPU_Null_fp_context; \
748  }
749
750#define _CPU_Context_save_fp( _fp_context ) \
751    _CPU_Save_float_context(*(_fp_context))
752
753#define _CPU_Context_restore_fp( _fp_context ) \
754    _CPU_Restore_float_context(*(_fp_context))
755
756extern void _CPU_Context_Initialize(
757  Context_Control  *_the_context,
758  uint32_t         *_stack_base,
759  uint32_t          _size,
760  uint32_t          _new_level,
761  void             *_entry_point,
762  boolean           _is_fp
763);
764
765/* end of Context handler macros */
766
767/* Fatal Error manager macros */
768
769/*
770 *  This routine copies _error into a known place -- typically a stack
771 *  location or a register, optionally disables interrupts, and
772 *  halts/stops the CPU.
773 */
774
775#define _CPU_Fatal_halt( _error ) \
776    _CPU_Fatal_error( _error )
777
778/* end of Fatal Error manager macros */
779
780/* Bitfield handler macros */
781
782/*
783 *  This routine sets _output to the bit number of the first bit
784 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
785 *  This type may be either 16 or 32 bits wide although only the 16
786 *  least significant bits will be used.
787 *
788 *  There are a number of variables in using a "find first bit" type
789 *  instruction.
790 *
791 *    (1) What happens when run on a value of zero?
792 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
793 *    (3) The numbering may be zero or one based.
794 *    (4) The "find first bit" instruction may search from MSB or LSB.
795 *
796 *  RTEMS guarantees that (1) will never happen so it is not a concern.
797 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
798 *  _CPU_Priority_bits_index().  These three form a set of routines
799 *  which must logically operate together.  Bits in the _value are
800 *  set and cleared based on masks built by _CPU_Priority_mask().
801 *  The basic major and minor values calculated by _Priority_Major()
802 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
803 *  to properly range between the values returned by the "find first bit"
804 *  instruction.  This makes it possible for _Priority_Get_highest() to
805 *  calculate the major and directly index into the minor table.
806 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
807 *  is the first bit found.
808 *
809 *  This entire "find first bit" and mapping process depends heavily
810 *  on the manner in which a priority is broken into a major and minor
811 *  components with the major being the 4 MSB of a priority and minor
812 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
813 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
814 *  to the lowest priority.
815 *
816 *  If your CPU does not have a "find first bit" instruction, then
817 *  there are ways to make do without it.  Here are a handful of ways
818 *  to implement this in software:
819 *
820 *    - a series of 16 bit test instructions
821 *    - a "binary search using if's"
822 *    - _number = 0
823 *      if _value > 0x00ff
824 *        _value >>=8
825 *        _number = 8;
826 *
827 *      if _value > 0x0000f
828 *        _value >=8
829 *        _number += 4
830 *
831 *      _number += bit_set_table[ _value ]
832 *
833 *    where bit_set_table[ 16 ] has values which indicate the first
834 *      bit set
835 */
836
837/*
838 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
839 *  dependencies on either a native bitscan instruction or an ffs() in the
840 *  C library.
841 */
842 
843#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
844#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
845 
846/* end of Bitfield handler macros */
847 
848/* Priority handler handler macros */
849 
850/*
851 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
852 *  dependencies on either a native bitscan instruction or an ffs() in the
853 *  C library.
854 */
855 
856/* end of Priority handler macros */
857
858/* functions */
859
860/*
861 *  _CPU_Initialize
862 *
863 *  This routine performs CPU dependent initialization.
864 */
865
866void _CPU_Initialize(
867  void      (*thread_dispatch)
868);
869
870/*
871 *  _CPU_ISR_install_raw_handler
872 *
873 *  This routine installs a "raw" interrupt handler directly into the
874 *  processor's vector table.
875 */
876 
877void _CPU_ISR_install_raw_handler(
878  uint32_t    vector,
879  proc_ptr    new_handler,
880  proc_ptr   *old_handler
881);
882
883/*
884 *  _CPU_ISR_install_vector
885 *
886 *  This routine installs an interrupt vector.
887 */
888
889void _CPU_ISR_install_vector(
890  uint32_t    vector,
891  proc_ptr    new_handler,
892  proc_ptr   *old_handler
893);
894
895/*
896 *  _CPU_Install_interrupt_stack
897 *
898 *  This routine installs the hardware interrupt stack pointer.
899 *
900 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
901 *         is TRUE.
902 */
903
904void _CPU_Install_interrupt_stack( void );
905
906/*
907 *  _CPU_Thread_Idle_body
908 *
909 *  This routine is the CPU dependent IDLE thread body.
910 *
911 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
912 *         is TRUE.
913 */
914
915void _CPU_Thread_Idle_body( void );
916
917/*
918 *  _CPU_Context_switch
919 *
920 *  This routine switches from the run context to the heir context.
921 */
922
923void _CPU_Context_switch(
924  Context_Control  *run,
925  Context_Control  *heir
926);
927
928/*
929 *  _CPU_Context_restore
930 *
931 *  This routine is generally used only to restart self in an
932 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
933 *
934 *  NOTE: May be unnecessary to reload some registers.
935 */
936
937void _CPU_Context_restore(
938  Context_Control *new_context
939);
940
941/*
942 *  _CPU_Save_float_context
943 *
944 *  This routine saves the floating point context passed to it.
945 */
946
947void _CPU_Save_float_context(
948  Context_Control_fp *fp_context_ptr
949);
950
951/*
952 *  _CPU_Restore_float_context
953 *
954 *  This routine restores the floating point context passed to it.
955 */
956
957void _CPU_Restore_float_context(
958  Context_Control_fp *fp_context_ptr
959);
960
961
962void _CPU_ISR_Set_signal_level(
963  uint32_t   level
964);
965
966void _CPU_Fatal_error(
967  uint32_t   _error
968);
969
970/*  The following routine swaps the endian format of an unsigned int.
971 *  It must be static because it is referenced indirectly.
972 *
973 *  This version will work on any processor, but if there is a better
974 *  way for your CPU PLEASE use it.  The most common way to do this is to:
975 *
976 *     swap least significant two bytes with 16-bit rotate
977 *     swap upper and lower 16-bits
978 *     swap most significant two bytes with 16-bit rotate
979 *
980 *  Some CPUs have special instructions which swap a 32-bit quantity in
981 *  a single instruction (e.g. i486).  It is probably best to avoid
982 *  an "endian swapping control bit" in the CPU.  One good reason is
983 *  that interrupts would probably have to be disabled to ensure that
984 *  an interrupt does not try to access the same "chunk" with the wrong
985 *  endian.  Another good reason is that on some CPUs, the endian bit
986 *  endianness for ALL fetches -- both code and data -- so the code
987 *  will be fetched incorrectly.
988 */
989 
990static inline uint32_t CPU_swap_u32(
991  uint32_t value
992)
993{
994  uint32_t   byte1, byte2, byte3, byte4, swapped;
995 
996  byte4 = (value >> 24) & 0xff;
997  byte3 = (value >> 16) & 0xff;
998  byte2 = (value >> 8)  & 0xff;
999  byte1 =  value        & 0xff;
1000 
1001  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1002  return( swapped );
1003}
1004
1005#define CPU_swap_u16( value ) \
1006  (((value&0xff) << 8) | ((value >> 8)&0xff))
1007
1008/*
1009 *  Special Purpose Routines to hide the use of UNIX system calls.
1010 */
1011
1012
1013/*
1014 *  Pointer to a sync io  Handler
1015 */
1016
1017typedef void ( *rtems_sync_io_handler )(
1018  int fd,
1019  boolean read,
1020  boolean wrtie,
1021  boolean except
1022);
1023
1024/* returns -1 if fd to large, 0 is successful */
1025int _CPU_Set_sync_io_handler(
1026  int fd,
1027  boolean read,
1028  boolean write,
1029  boolean except,
1030  rtems_sync_io_handler handler
1031);
1032
1033/* returns -1 if fd to large, o if successful */
1034int _CPU_Clear_sync_io_handler(
1035  int fd
1036);
1037
1038int _CPU_Get_clock_vector( void );
1039
1040void _CPU_Start_clock(
1041  int microseconds
1042);
1043
1044void _CPU_Stop_clock( void );
1045
1046#if defined(RTEMS_MULTIPROCESSING)
1047
1048void _CPU_SHM_Init(
1049  uint32_t     maximum_nodes,
1050  boolean      is_master_node,
1051  void       **shm_address,
1052  uint32_t    *shm_length
1053);
1054
1055int _CPU_Get_pid( void );
1056 
1057int _CPU_SHM_Get_vector( void );
1058 
1059void _CPU_SHM_Send_interrupt(
1060  int pid,
1061  int vector
1062);
1063 
1064void _CPU_SHM_Lock(
1065  int semaphore
1066);
1067
1068void _CPU_SHM_Unlock(
1069  int semaphore
1070);
1071#endif
1072
1073#ifdef __cplusplus
1074}
1075#endif
1076
1077#endif
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