source: rtems/cpukit/score/cpu/unix/rtems/score/cpu.h @ c54152a2

4.104.114.84.95
Last change on this file since c54152a2 was c54152a2, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 25, 2001 at 6:45:59 PM

2001-01-25 Joel Sherrill <joel@…>

  • cpu.c, rtems/score/cpu.h: Bug report from Peter Mueller <peter.o.mueller@…> because of not correcting for the ISR vector table now being allocated from the workspace.
  • Property mode set to 100644
File size: 32.4 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14
15#ifndef __CPU_h
16#define __CPU_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems/score/unix.h>              /* pick up machine definitions */
23#ifndef ASM
24#include <rtems/score/unixtypes.h>
25#endif
26
27#include <rtems/score/unixsize.h>
28
29#if defined(solaris2)
30#undef  _POSIX_C_SOURCE
31#define _POSIX_C_SOURCE 3
32#undef  __STRICT_ANSI__
33#define __STRICT_ANSI__
34#endif
35
36#if defined(linux)
37#define MALLOC_0_RETURNS_NULL
38#endif
39
40/* conditional compilation parameters */
41
42/*
43 *  Should the calls to _Thread_Enable_dispatch be inlined?
44 *
45 *  If TRUE, then they are inlined.
46 *  If FALSE, then a subroutine call is made.
47 *
48 *  Basically this is an example of the classic trade-off of size
49 *  versus speed.  Inlining the call (TRUE) typically increases the
50 *  size of RTEMS while speeding up the enabling of dispatching.
51 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
52 *  only be 0 or 1 unless you are in an interrupt handler and that
53 *  interrupt handler invokes the executive.]  When not inlined
54 *  something calls _Thread_Enable_dispatch which in turns calls
55 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
56 *  one subroutine call is avoided entirely.]
57 */
58
59#define CPU_INLINE_ENABLE_DISPATCH       FALSE
60
61/*
62 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
63 *  be unrolled one time?  In unrolled each iteration of the loop examines
64 *  two "nodes" on the chain being searched.  Otherwise, only one node
65 *  is examined per iteration.
66 *
67 *  If TRUE, then the loops are unrolled.
68 *  If FALSE, then the loops are not unrolled.
69 *
70 *  The primary factor in making this decision is the cost of disabling
71 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
72 *  body of the loop.  On some CPUs, the flash is more expensive than
73 *  one iteration of the loop body.  In this case, it might be desirable
74 *  to unroll the loop.  It is important to note that on some CPUs, this
75 *  code is the longest interrupt disable period in RTEMS.  So it is
76 *  necessary to strike a balance when setting this parameter.
77 */
78
79#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
80
81/*
82 *  Does RTEMS manage a dedicated interrupt stack in software?
83 *
84 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
85 *  If FALSE, nothing is done.
86 *
87 *  If the CPU supports a dedicated interrupt stack in hardware,
88 *  then it is generally the responsibility of the BSP to allocate it
89 *  and set it up.
90 *
91 *  If the CPU does not support a dedicated interrupt stack, then
92 *  the porter has two options: (1) execute interrupts on the
93 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
94 *  interrupt stack.
95 *
96 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
97 *
98 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
99 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
100 *  possible that both are FALSE for a particular CPU.  Although it
101 *  is unclear what that would imply about the interrupt processing
102 *  procedure on that CPU.
103 */
104
105#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
106
107/*
108 *  Does this CPU have hardware support for a dedicated interrupt stack?
109 *
110 *  If TRUE, then it must be installed during initialization.
111 *  If FALSE, then no installation is performed.
112 *
113 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
114 *
115 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
116 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
117 *  possible that both are FALSE for a particular CPU.  Although it
118 *  is unclear what that would imply about the interrupt processing
119 *  procedure on that CPU.
120 */
121
122#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
123
124/*
125 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
126 *
127 *  If TRUE, then the memory is allocated during initialization.
128 *  If FALSE, then the memory is allocated during initialization.
129 *
130 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
131 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
132 */
133
134#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
135
136/*
137 *  Does the RTEMS invoke the user's ISR with the vector number and
138 *  a pointer to the saved interrupt frame (1) or just the vector
139 *  number (0)?
140 */
141
142#define CPU_ISR_PASSES_FRAME_POINTER 0
143
144/*
145 *  Does the CPU have hardware floating point?
146 *
147 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
148 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
149 *
150 *  If there is a FP coprocessor such as the i387 or mc68881, then
151 *  the answer is TRUE.
152 *
153 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
154 *  It indicates whether or not this CPU model has FP support.  For
155 *  example, it would be possible to have an i386_nofp CPU model
156 *  which set this to false to indicate that you have an i386 without
157 *  an i387 and wish to leave floating point support out of RTEMS.
158 */
159
160#define CPU_HARDWARE_FP     TRUE
161#define CPU_SOFTWARE_FP     FALSE
162
163/*
164 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
165 *
166 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
167 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
168 *
169 *  So far, the only CPU in which this option has been used is the
170 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
171 *  floating point registers to perform integer multiplies.  If
172 *  a function which you would not think utilize the FP unit DOES,
173 *  then one can not easily predict which tasks will use the FP hardware.
174 *  In this case, this option should be TRUE.
175 *
176 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
177 */
178
179#define CPU_ALL_TASKS_ARE_FP     FALSE
180
181/*
182 *  Should the IDLE task have a floating point context?
183 *
184 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
185 *  and it has a floating point context which is switched in and out.
186 *  If FALSE, then the IDLE task does not have a floating point context.
187 *
188 *  Setting this to TRUE negatively impacts the time required to preempt
189 *  the IDLE task from an interrupt because the floating point context
190 *  must be saved as part of the preemption.
191 */
192
193#define CPU_IDLE_TASK_IS_FP      FALSE
194
195/*
196 *  Should the saving of the floating point registers be deferred
197 *  until a context switch is made to another different floating point
198 *  task?
199 *
200 *  If TRUE, then the floating point context will not be stored until
201 *  necessary.  It will remain in the floating point registers and not
202 *  disturned until another floating point task is switched to.
203 *
204 *  If FALSE, then the floating point context is saved when a floating
205 *  point task is switched out and restored when the next floating point
206 *  task is restored.  The state of the floating point registers between
207 *  those two operations is not specified.
208 *
209 *  If the floating point context does NOT have to be saved as part of
210 *  interrupt dispatching, then it should be safe to set this to TRUE.
211 *
212 *  Setting this flag to TRUE results in using a different algorithm
213 *  for deciding when to save and restore the floating point context.
214 *  The deferred FP switch algorithm minimizes the number of times
215 *  the FP context is saved and restored.  The FP context is not saved
216 *  until a context switch is made to another, different FP task.
217 *  Thus in a system with only one FP task, the FP context will never
218 *  be saved or restored.
219 */
220
221#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
222
223/*
224 *  Does this port provide a CPU dependent IDLE task implementation?
225 *
226 *  If TRUE, then the routine _CPU_Thread_Idle_body
227 *  must be provided and is the default IDLE thread body instead of
228 *  _CPU_Thread_Idle_body.
229 *
230 *  If FALSE, then use the generic IDLE thread body if the BSP does
231 *  not provide one.
232 *
233 *  This is intended to allow for supporting processors which have
234 *  a low power or idle mode.  When the IDLE thread is executed, then
235 *  the CPU can be powered down.
236 *
237 *  The order of precedence for selecting the IDLE thread body is:
238 *
239 *    1.  BSP provided
240 *    2.  CPU dependent (if provided)
241 *    3.  generic (if no BSP and no CPU dependent)
242 */
243
244#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
245
246/*
247 *  Does the stack grow up (toward higher addresses) or down
248 *  (toward lower addresses)?
249 *
250 *  If TRUE, then the grows upward.
251 *  If FALSE, then the grows toward smaller addresses.
252 */
253
254#if defined(__hppa__)
255#define CPU_STACK_GROWS_UP               TRUE
256#elif defined(__sparc__) || defined(__i386__)
257#define CPU_STACK_GROWS_UP               FALSE
258#else
259#error "unknown CPU!!"
260#endif
261
262
263/*
264 *  The following is the variable attribute used to force alignment
265 *  of critical RTEMS structures.  On some processors it may make
266 *  sense to have these aligned on tighter boundaries than
267 *  the minimum requirements of the compiler in order to have as
268 *  much of the critical data area as possible in a cache line.
269 *
270 *  The placement of this macro in the declaration of the variables
271 *  is based on the syntactically requirements of the GNU C
272 *  "__attribute__" extension.  For example with GNU C, use
273 *  the following to force a structures to a 32 byte boundary.
274 *
275 *      __attribute__ ((aligned (32)))
276 *
277 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
278 *         To benefit from using this, the data must be heavily
279 *         used so it will stay in the cache and used frequently enough
280 *         in the executive to justify turning this on.
281 */
282
283#ifdef __GNUC__
284#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
285#else
286#define CPU_STRUCTURE_ALIGNMENT
287#endif
288
289/*
290 *  Define what is required to specify how the network to host conversion
291 *  routines are handled.
292 */
293
294#if defined(__hppa__) || defined(__sparc__)
295#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
296#define CPU_BIG_ENDIAN                           TRUE
297#define CPU_LITTLE_ENDIAN                        FALSE
298#elif defined(__i386__)
299#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
300#define CPU_BIG_ENDIAN                           FALSE
301#define CPU_LITTLE_ENDIAN                        TRUE
302#else
303#error "Unknown CPU!!!"
304#endif
305
306/*
307 *  The following defines the number of bits actually used in the
308 *  interrupt field of the task mode.  How those bits map to the
309 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
310 */
311
312#define CPU_MODES_INTERRUPT_MASK   0x00000001
313
314#define CPU_NAME "UNIX"
315
316/*
317 *  Processor defined structures
318 *
319 *  Examples structures include the descriptor tables from the i386
320 *  and the processor control structure on the i960ca.
321 */
322
323/* may need to put some structures here.  */
324
325#if defined(__hppa__)
326/*
327 * Word indices within a jmp_buf structure
328 */
329
330#ifdef RTEMS_NEWLIB_SETJMP
331#define RP_OFF       6
332#define SP_OFF       2
333#define R3_OFF      10
334#define R4_OFF      11
335#define R5_OFF      12
336#define R6_OFF      13
337#define R7_OFF      14
338#define R8_OFF      15
339#define R9_OFF      16
340#define R10_OFF     17
341#define R11_OFF     18
342#define R12_OFF     19
343#define R13_OFF     20
344#define R14_OFF     21
345#define R15_OFF     22
346#define R16_OFF     23
347#define R17_OFF     24
348#define R18_OFF     25
349#define DP_OFF      26
350#endif
351
352#ifdef RTEMS_UNIXLIB_SETJMP
353#define RP_OFF       0
354#define SP_OFF       1
355#define R3_OFF       4
356#define R4_OFF       5
357#define R5_OFF       6
358#define R6_OFF       7
359#define R7_OFF       8
360#define R8_OFF       9
361#define R9_OFF      10
362#define R10_OFF     11
363#define R11_OFF     12
364#define R12_OFF     13
365#define R13_OFF     14
366#define R14_OFF     15
367#define R15_OFF     16
368#define R16_OFF     17
369#define R17_OFF     18
370#define R18_OFF     19
371#define DP_OFF      20
372#endif
373#endif
374
375#if defined(__i386__)
376 
377#ifdef RTEMS_NEWLIB
378#error "Newlib not installed"
379#endif
380 
381/*
382 *  For i386 targets
383 */
384 
385#ifdef RTEMS_UNIXLIB
386#if defined(__FreeBSD__)
387#define RET_OFF    0
388#define EBX_OFF    1
389#define EBP_OFF    2
390#define ESP_OFF    3
391#define ESI_OFF    4
392#define EDI_OFF    5
393#elif defined(__CYGWIN__)
394#define EAX_OFF    0
395#define EBX_OFF    1
396#define ECX_OFF    2
397#define EDX_OFF    3
398#define ESI_OFF    4
399#define EDI_OFF    5
400#define EBP_OFF    6
401#define ESP_OFF    7
402#define RET_OFF    8
403#else
404/* Linux */
405#define EBX_OFF    0
406#define ESI_OFF    1
407#define EDI_OFF    2
408#define EBP_OFF    3
409#define ESP_OFF    4
410#define RET_OFF    5
411#endif
412#endif
413 
414#endif
415 
416#if defined(__sparc__)
417
418/*
419 *  Word indices within a jmp_buf structure
420 */
421 
422#ifdef RTEMS_NEWLIB
423#define ADDR_ADJ_OFFSET -8
424#define SP_OFF    0
425#define RP_OFF    1
426#define FP_OFF    2
427#endif
428
429#ifdef RTEMS_UNIXLIB
430#define ADDR_ADJ_OFFSET 0
431#define G0_OFF    0
432#define SP_OFF    1
433#define RP_OFF    2   
434#define FP_OFF    3
435#define I7_OFF    4
436#endif
437
438#endif
439
440/*
441 * Contexts
442 *
443 *  Generally there are 2 types of context to save.
444 *     1. Interrupt registers to save
445 *     2. Task level registers to save
446 *
447 *  This means we have the following 3 context items:
448 *     1. task level context stuff::  Context_Control
449 *     2. floating point task stuff:: Context_Control_fp
450 *     3. special interrupt level context :: Context_Control_interrupt
451 *
452 *  On some processors, it is cost-effective to save only the callee
453 *  preserved registers during a task context switch.  This means
454 *  that the ISR code needs to save those registers which do not
455 *  persist across function calls.  It is not mandatory to make this
456 *  distinctions between the caller/callee saves registers for the
457 *  purpose of minimizing context saved during task switch and on interrupts.
458 *  If the cost of saving extra registers is minimal, simplicity is the
459 *  choice.  Save the same context on interrupt entry as for tasks in
460 *  this case.
461 *
462 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
463 *  care should be used in designing the context area.
464 *
465 *  On some CPUs with hardware floating point support, the Context_Control_fp
466 *  structure will not be used or it simply consist of an array of a
467 *  fixed number of bytes.   This is done when the floating point context
468 *  is dumped by a "FP save context" type instruction and the format
469 *  is not really defined by the CPU.  In this case, there is no need
470 *  to figure out the exact format -- only the size.  Of course, although
471 *  this is enough information for RTEMS, it is probably not enough for
472 *  a debugger such as gdb.  But that is another problem.
473 */
474
475/*
476 *  This is really just the area for the following fields.
477 *
478 *    jmp_buf    regs;
479 *    unsigned32 isr_level;
480 *
481 *  Doing it this way avoids conflicts between the native stuff and the
482 *  RTEMS stuff.
483 *
484 *  NOTE:
485 *      hpux9 setjmp is optimized for the case where the setjmp buffer
486 *      is 8 byte aligned.  In a RISC world, this seems likely to enable
487 *      8 byte copies, especially for the float registers.
488 *      So we always align them on 8 byte boundaries.
489 */
490
491#ifdef __GNUC__
492#define CONTEXT_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (8)))
493#else
494#define CONTEXT_STRUCTURE_ALIGNMENT
495#endif
496
497typedef struct {
498  char      Area[ CPU_CONTEXT_SIZE_IN_BYTES ] CONTEXT_STRUCTURE_ALIGNMENT;
499} Context_Control;
500
501typedef struct {
502} Context_Control_fp;
503
504typedef struct {
505} CPU_Interrupt_frame;
506
507
508/*
509 *  The following table contains the information required to configure
510 *  the UNIX Simulator specific parameters.
511 */
512
513typedef struct {
514  void       (*pretasking_hook)( void );
515  void       (*predriver_hook)( void );
516  void       (*postdriver_hook)( void );
517  void       (*idle_task)( void );
518  boolean      do_zero_of_workspace;
519  unsigned32   idle_task_stack_size;
520  unsigned32   interrupt_stack_size;
521  unsigned32   extra_mpci_receive_server_stack;
522  void *     (*stack_allocate_hook)( unsigned32 );
523  void       (*stack_free_hook)( void* );
524  /* end of required fields */
525}   rtems_cpu_table;
526
527/*
528 *  Macros to access required entires in the CPU Table are in
529 *  the file rtems/system.h.
530 */
531
532/*
533 *  Macros to access UNIX specific additions to the CPU Table
534 */
535
536/* There are no CPU specific additions to the CPU Table for this port. */
537
538/*
539 *  This variable is optional.  It is used on CPUs on which it is difficult
540 *  to generate an "uninitialized" FP context.  It is filled in by
541 *  _CPU_Initialize and copied into the task's FP context area during
542 *  _CPU_Context_Initialize.
543 */
544
545SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
546
547/*
548 *  On some CPUs, RTEMS supports a software managed interrupt stack.
549 *  This stack is allocated by the Interrupt Manager and the switch
550 *  is performed in _ISR_Handler.  These variables contain pointers
551 *  to the lowest and highest addresses in the chunk of memory allocated
552 *  for the interrupt stack.  Since it is unknown whether the stack
553 *  grows up or down (in general), this give the CPU dependent
554 *  code the option of picking the version it wants to use.
555 *
556 *  NOTE: These two variables are required if the macro
557 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
558 */
559
560SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
561SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
562
563/*
564 *  With some compilation systems, it is difficult if not impossible to
565 *  call a high-level language routine from assembly language.  This
566 *  is especially true of commercial Ada compilers and name mangling
567 *  C++ ones.  This variable can be optionally defined by the CPU porter
568 *  and contains the address of the routine _Thread_Dispatch.  This
569 *  can make it easier to invoke that routine at the end of the interrupt
570 *  sequence (if a dispatch is necessary).
571 */
572
573SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
574
575/*
576 *  Nothing prevents the porter from declaring more CPU specific variables.
577 */
578
579/* XXX: if needed, put more variables here */
580
581/*
582 *  The size of the floating point context area.  On some CPUs this
583 *  will not be a "sizeof" because the format of the floating point
584 *  area is not defined -- only the size is.  This is usually on
585 *  CPUs with a "floating point save context" instruction.
586 */
587
588#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
589
590/*
591 * The size of a frame on the stack
592 */
593
594#if defined(__hppa__)
595#define CPU_FRAME_SIZE  (32 * 4)
596#elif defined(__sparc__)
597#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
598#elif defined(__i386__)
599#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
600#else
601#error "Unknown CPU!!!"
602#endif
603
604/*
605 *  Amount of extra stack (above minimum stack size) required by
606 *  MPCI receive server thread.  Remember that in a multiprocessor
607 *  system this thread must exist and be able to process all directives.
608 */
609
610#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
611
612/*
613 *  This defines the number of entries in the ISR_Vector_table managed
614 *  by RTEMS.
615 */
616
617#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
618#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
619
620/*
621 *  Should be large enough to run all RTEMS tests.  This insures
622 *  that a "reasonable" small application should not have any problems.
623 */
624
625#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
626
627/*
628 *  CPU's worst alignment requirement for data types on a byte boundary.  This
629 *  alignment does not take into account the requirements for the stack.
630 */
631
632#define CPU_ALIGNMENT              8
633
634/*
635 *  This number corresponds to the byte alignment requirement for the
636 *  heap handler.  This alignment requirement may be stricter than that
637 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
638 *  common for the heap to follow the same alignment requirement as
639 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
640 *  then this should be set to CPU_ALIGNMENT.
641 *
642 *  NOTE:  This does not have to be a power of 2.  It does have to
643 *         be greater or equal to than CPU_ALIGNMENT.
644 */
645
646#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
647
648/*
649 *  This number corresponds to the byte alignment requirement for memory
650 *  buffers allocated by the partition manager.  This alignment requirement
651 *  may be stricter than that for the data types alignment specified by
652 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
653 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
654 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
655 *
656 *  NOTE:  This does not have to be a power of 2.  It does have to
657 *         be greater or equal to than CPU_ALIGNMENT.
658 */
659
660#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
661
662/*
663 *  This number corresponds to the byte alignment requirement for the
664 *  stack.  This alignment requirement may be stricter than that for the
665 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
666 *  is strict enough for the stack, then this should be set to 0.
667 *
668 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
669 */
670
671#define CPU_STACK_ALIGNMENT        64
672
673/*
674 *  ISR handler macros
675 */
676
677/*
678 *  Support routine to initialize the RTEMS vector table after it is allocated.
679 */
680
681void _CPU_Initialize_vectors(void);
682
683/*
684 *  Disable all interrupts for an RTEMS critical section.  The previous
685 *  level is returned in _level.
686 */
687
688extern unsigned32 _CPU_ISR_Disable_support(void);
689
690#define _CPU_ISR_Disable( _level ) \
691    do { \
692      (_level) = _CPU_ISR_Disable_support(); \
693    } while ( 0 )
694
695/*
696 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
697 *  This indicates the end of an RTEMS critical section.  The parameter
698 *  _level is not modified.
699 */
700
701void _CPU_ISR_Enable(unsigned32 level);
702
703/*
704 *  This temporarily restores the interrupt to _level before immediately
705 *  disabling them again.  This is used to divide long RTEMS critical
706 *  sections into two or more parts.  The parameter _level is not
707 * modified.
708 */
709
710#define _CPU_ISR_Flash( _level ) \
711  do { \
712      register unsigned32 _ignored = 0; \
713      _CPU_ISR_Enable( (_level) ); \
714      _CPU_ISR_Disable( _ignored ); \
715  } while ( 0 )
716
717/*
718 *  Map interrupt level in task mode onto the hardware that the CPU
719 *  actually provides.  Currently, interrupt levels which do not
720 *  map onto the CPU in a generic fashion are undefined.  Someday,
721 *  it would be nice if these were "mapped" by the application
722 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
723 *  8 - 255 would be available for bsp/application specific meaning.
724 *  This could be used to manage a programmable interrupt controller
725 *  via the rtems_task_mode directive.
726 */
727
728#define _CPU_ISR_Set_level( new_level ) \
729  { \
730    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
731    else                  _CPU_ISR_Enable( 1 ); \
732  }
733
734unsigned32 _CPU_ISR_Get_level( void );
735
736/* end of ISR handler macros */
737
738/* Context handler macros */
739
740/*
741 *  This routine is responsible for somehow restarting the currently
742 *  executing task.  If you are lucky, then all that is necessary
743 *  is restoring the context.  Otherwise, there will need to be
744 *  a special assembly routine which does something special in this
745 *  case.  Context_Restore should work most of the time.  It will
746 *  not work if restarting self conflicts with the stack frame
747 *  assumptions of restoring a context.
748 */
749
750#define _CPU_Context_Restart_self( _the_context ) \
751   _CPU_Context_restore( (_the_context) );
752
753/*
754 *  The purpose of this macro is to allow the initial pointer into
755 *  a floating point context area (used to save the floating point
756 *  context) to be at an arbitrary place in the floating point
757 *  context area.
758 *
759 *  This is necessary because some FP units are designed to have
760 *  their context saved as a stack which grows into lower addresses.
761 *  Other FP units can be saved by simply moving registers into offsets
762 *  from the base of the context area.  Finally some FP units provide
763 *  a "dump context" instruction which could fill in from high to low
764 *  or low to high based on the whim of the CPU designers.
765 */
766
767#define _CPU_Context_Fp_start( _base, _offset ) \
768   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
769
770/*
771 *  This routine initializes the FP context area passed to it to.
772 *  There are a few standard ways in which to initialize the
773 *  floating point context.  The code included for this macro assumes
774 *  that this is a CPU in which a "initial" FP context was saved into
775 *  _CPU_Null_fp_context and it simply copies it to the destination
776 *  context passed to it.
777 *
778 *  Other models include (1) not doing anything, and (2) putting
779 *  a "null FP status word" in the correct place in the FP context.
780 */
781
782#define _CPU_Context_Initialize_fp( _destination ) \
783  { \
784   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
785  }
786
787#define _CPU_Context_save_fp( _fp_context ) \
788    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
789
790#define _CPU_Context_restore_fp( _fp_context ) \
791    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
792
793extern void _CPU_Context_Initialize(
794  Context_Control  *_the_context,
795  unsigned32       *_stack_base,
796  unsigned32        _size,
797  unsigned32        _new_level,
798  void             *_entry_point,
799  boolean           _is_fp
800);
801
802/* end of Context handler macros */
803
804/* Fatal Error manager macros */
805
806/*
807 *  This routine copies _error into a known place -- typically a stack
808 *  location or a register, optionally disables interrupts, and
809 *  halts/stops the CPU.
810 */
811
812#define _CPU_Fatal_halt( _error ) \
813    _CPU_Fatal_error( _error )
814
815/* end of Fatal Error manager macros */
816
817/* Bitfield handler macros */
818
819/*
820 *  This routine sets _output to the bit number of the first bit
821 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
822 *  This type may be either 16 or 32 bits wide although only the 16
823 *  least significant bits will be used.
824 *
825 *  There are a number of variables in using a "find first bit" type
826 *  instruction.
827 *
828 *    (1) What happens when run on a value of zero?
829 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
830 *    (3) The numbering may be zero or one based.
831 *    (4) The "find first bit" instruction may search from MSB or LSB.
832 *
833 *  RTEMS guarantees that (1) will never happen so it is not a concern.
834 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
835 *  _CPU_Priority_bits_index().  These three form a set of routines
836 *  which must logically operate together.  Bits in the _value are
837 *  set and cleared based on masks built by _CPU_Priority_mask().
838 *  The basic major and minor values calculated by _Priority_Major()
839 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
840 *  to properly range between the values returned by the "find first bit"
841 *  instruction.  This makes it possible for _Priority_Get_highest() to
842 *  calculate the major and directly index into the minor table.
843 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
844 *  is the first bit found.
845 *
846 *  This entire "find first bit" and mapping process depends heavily
847 *  on the manner in which a priority is broken into a major and minor
848 *  components with the major being the 4 MSB of a priority and minor
849 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
850 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
851 *  to the lowest priority.
852 *
853 *  If your CPU does not have a "find first bit" instruction, then
854 *  there are ways to make do without it.  Here are a handful of ways
855 *  to implement this in software:
856 *
857 *    - a series of 16 bit test instructions
858 *    - a "binary search using if's"
859 *    - _number = 0
860 *      if _value > 0x00ff
861 *        _value >>=8
862 *        _number = 8;
863 *
864 *      if _value > 0x0000f
865 *        _value >=8
866 *        _number += 4
867 *
868 *      _number += bit_set_table[ _value ]
869 *
870 *    where bit_set_table[ 16 ] has values which indicate the first
871 *      bit set
872 */
873
874/*
875 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
876 *  dependencies on either a native bitscan instruction or an ffs() in the
877 *  C library.
878 */
879 
880#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
881#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
882 
883/* end of Bitfield handler macros */
884 
885/* Priority handler handler macros */
886 
887/*
888 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
889 *  dependencies on either a native bitscan instruction or an ffs() in the
890 *  C library.
891 */
892 
893/* end of Priority handler macros */
894
895/* functions */
896
897/*
898 *  _CPU_Initialize
899 *
900 *  This routine performs CPU dependent initialization.
901 */
902
903void _CPU_Initialize(
904  rtems_cpu_table  *cpu_table,
905  void      (*thread_dispatch)
906);
907
908/*
909 *  _CPU_ISR_install_raw_handler
910 *
911 *  This routine installs a "raw" interrupt handler directly into the
912 *  processor's vector table.
913 */
914 
915void _CPU_ISR_install_raw_handler(
916  unsigned32  vector,
917  proc_ptr    new_handler,
918  proc_ptr   *old_handler
919);
920
921/*
922 *  _CPU_ISR_install_vector
923 *
924 *  This routine installs an interrupt vector.
925 */
926
927void _CPU_ISR_install_vector(
928  unsigned32  vector,
929  proc_ptr    new_handler,
930  proc_ptr   *old_handler
931);
932
933/*
934 *  _CPU_Install_interrupt_stack
935 *
936 *  This routine installs the hardware interrupt stack pointer.
937 *
938 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
939 *         is TRUE.
940 */
941
942void _CPU_Install_interrupt_stack( void );
943
944/*
945 *  _CPU_Thread_Idle_body
946 *
947 *  This routine is the CPU dependent IDLE thread body.
948 *
949 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
950 *         is TRUE.
951 */
952
953void _CPU_Thread_Idle_body( void );
954
955/*
956 *  _CPU_Context_switch
957 *
958 *  This routine switches from the run context to the heir context.
959 */
960
961void _CPU_Context_switch(
962  Context_Control  *run,
963  Context_Control  *heir
964);
965
966/*
967 *  _CPU_Context_restore
968 *
969 *  This routine is generally used only to restart self in an
970 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
971 *
972 *  NOTE: May be unnecessary to reload some registers.
973 */
974
975void _CPU_Context_restore(
976  Context_Control *new_context
977);
978
979/*
980 *  _CPU_Save_float_context
981 *
982 *  This routine saves the floating point context passed to it.
983 */
984
985void _CPU_Save_float_context(
986  Context_Control_fp *fp_context_ptr
987);
988
989/*
990 *  _CPU_Restore_float_context
991 *
992 *  This routine restores the floating point context passed to it.
993 */
994
995void _CPU_Restore_float_context(
996  Context_Control_fp *fp_context_ptr
997);
998
999
1000void _CPU_ISR_Set_signal_level(
1001  unsigned32 level
1002);
1003
1004void _CPU_Fatal_error(
1005  unsigned32 _error
1006);
1007
1008/*  The following routine swaps the endian format of an unsigned int.
1009 *  It must be static because it is referenced indirectly.
1010 *
1011 *  This version will work on any processor, but if there is a better
1012 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1013 *
1014 *     swap least significant two bytes with 16-bit rotate
1015 *     swap upper and lower 16-bits
1016 *     swap most significant two bytes with 16-bit rotate
1017 *
1018 *  Some CPUs have special instructions which swap a 32-bit quantity in
1019 *  a single instruction (e.g. i486).  It is probably best to avoid
1020 *  an "endian swapping control bit" in the CPU.  One good reason is
1021 *  that interrupts would probably have to be disabled to insure that
1022 *  an interrupt does not try to access the same "chunk" with the wrong
1023 *  endian.  Another good reason is that on some CPUs, the endian bit
1024 *  endianness for ALL fetches -- both code and data -- so the code
1025 *  will be fetched incorrectly.
1026 */
1027 
1028static inline unsigned int CPU_swap_u32(
1029  unsigned int value
1030)
1031{
1032  unsigned32 byte1, byte2, byte3, byte4, swapped;
1033 
1034  byte4 = (value >> 24) & 0xff;
1035  byte3 = (value >> 16) & 0xff;
1036  byte2 = (value >> 8)  & 0xff;
1037  byte1 =  value        & 0xff;
1038 
1039  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1040  return( swapped );
1041}
1042
1043#define CPU_swap_u16( value ) \
1044  (((value&0xff) << 8) | ((value >> 8)&0xff))
1045
1046/*
1047 *  Special Purpose Routines to hide the use of UNIX system calls.
1048 */
1049
1050
1051/*
1052 *  Pointer to a sync io  Handler
1053 */
1054
1055typedef void ( *rtems_sync_io_handler )(
1056  int fd,
1057  boolean read,
1058  boolean wrtie,
1059  boolean except
1060);
1061
1062/* returns -1 if fd to large, 0 is successful */
1063int _CPU_Set_sync_io_handler(
1064  int fd,
1065  boolean read,
1066  boolean write,
1067  boolean except,
1068  rtems_sync_io_handler handler
1069);
1070
1071/* returns -1 if fd to large, o if successful */
1072int _CPU_Clear_sync_io_handler(
1073  int fd
1074);
1075
1076int _CPU_Get_clock_vector( void );
1077
1078void _CPU_Start_clock( 
1079  int microseconds
1080);
1081
1082void _CPU_Stop_clock( void );
1083
1084#if defined(RTEMS_MULTIPROCESSING)
1085
1086void _CPU_SHM_Init( 
1087  unsigned32   maximum_nodes,
1088  boolean      is_master_node,
1089  void       **shm_address,
1090  unsigned32  *shm_length
1091);
1092
1093int _CPU_Get_pid( void );
1094 
1095int _CPU_SHM_Get_vector( void );
1096 
1097void _CPU_SHM_Send_interrupt(
1098  int pid,
1099  int vector
1100);
1101 
1102void _CPU_SHM_Lock( 
1103  int semaphore
1104);
1105
1106void _CPU_SHM_Unlock(
1107  int semaphore
1108);
1109#endif
1110
1111#ifdef __cplusplus
1112}
1113#endif
1114
1115#endif
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