source: rtems/cpukit/score/cpu/unix/rtems/score/cpu.h @ c346f33d

4.104.114.84.95
Last change on this file since c346f33d was c346f33d, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 30, 2004 at 11:49:14 AM

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • cpu.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 32.2 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the
4 *  UNIX port of RTEMS.
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  $Id$
13 */
14
15#ifndef __CPU_h
16#define __CPU_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems/score/unix.h>              /* pick up machine definitions */
23#ifndef ASM
24#include <rtems/score/types.h>
25#endif
26
27#include <rtems/score/unixsize.h>
28
29#if defined(solaris2)
30#undef  _POSIX_C_SOURCE
31#define _POSIX_C_SOURCE 3
32#endif
33
34#if defined(linux)
35#define MALLOC_0_RETURNS_NULL
36#endif
37
38/* conditional compilation parameters */
39
40/*
41 *  Should the calls to _Thread_Enable_dispatch be inlined?
42 *
43 *  If TRUE, then they are inlined.
44 *  If FALSE, then a subroutine call is made.
45 *
46 *  Basically this is an example of the classic trade-off of size
47 *  versus speed.  Inlining the call (TRUE) typically increases the
48 *  size of RTEMS while speeding up the enabling of dispatching.
49 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
50 *  only be 0 or 1 unless you are in an interrupt handler and that
51 *  interrupt handler invokes the executive.]  When not inlined
52 *  something calls _Thread_Enable_dispatch which in turns calls
53 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
54 *  one subroutine call is avoided entirely.]
55 */
56
57#define CPU_INLINE_ENABLE_DISPATCH       FALSE
58
59/*
60 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
61 *  be unrolled one time?  In unrolled each iteration of the loop examines
62 *  two "nodes" on the chain being searched.  Otherwise, only one node
63 *  is examined per iteration.
64 *
65 *  If TRUE, then the loops are unrolled.
66 *  If FALSE, then the loops are not unrolled.
67 *
68 *  The primary factor in making this decision is the cost of disabling
69 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
70 *  body of the loop.  On some CPUs, the flash is more expensive than
71 *  one iteration of the loop body.  In this case, it might be desirable
72 *  to unroll the loop.  It is important to note that on some CPUs, this
73 *  code is the longest interrupt disable period in RTEMS.  So it is
74 *  necessary to strike a balance when setting this parameter.
75 */
76
77#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
78
79/*
80 *  Does RTEMS manage a dedicated interrupt stack in software?
81 *
82 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
83 *  If FALSE, nothing is done.
84 *
85 *  If the CPU supports a dedicated interrupt stack in hardware,
86 *  then it is generally the responsibility of the BSP to allocate it
87 *  and set it up.
88 *
89 *  If the CPU does not support a dedicated interrupt stack, then
90 *  the porter has two options: (1) execute interrupts on the
91 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
92 *  interrupt stack.
93 *
94 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
95 *
96 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
97 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
98 *  possible that both are FALSE for a particular CPU.  Although it
99 *  is unclear what that would imply about the interrupt processing
100 *  procedure on that CPU.
101 */
102
103#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
104
105/*
106 *  Does this CPU have hardware support for a dedicated interrupt stack?
107 *
108 *  If TRUE, then it must be installed during initialization.
109 *  If FALSE, then no installation is performed.
110 *
111 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
112 *
113 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
114 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
115 *  possible that both are FALSE for a particular CPU.  Although it
116 *  is unclear what that would imply about the interrupt processing
117 *  procedure on that CPU.
118 */
119
120#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
121
122/*
123 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
124 *
125 *  If TRUE, then the memory is allocated during initialization.
126 *  If FALSE, then the memory is allocated during initialization.
127 *
128 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
129 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
130 */
131
132#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
133
134/*
135 *  Does the RTEMS invoke the user's ISR with the vector number and
136 *  a pointer to the saved interrupt frame (1) or just the vector
137 *  number (0)?
138 */
139
140#define CPU_ISR_PASSES_FRAME_POINTER 0
141
142/*
143 *  Does the CPU have hardware floating point?
144 *
145 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
146 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
147 *
148 *  If there is a FP coprocessor such as the i387 or mc68881, then
149 *  the answer is TRUE.
150 *
151 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
152 *  It indicates whether or not this CPU model has FP support.  For
153 *  example, it would be possible to have an i386_nofp CPU model
154 *  which set this to false to indicate that you have an i386 without
155 *  an i387 and wish to leave floating point support out of RTEMS.
156 */
157
158#define CPU_HARDWARE_FP     TRUE
159#define CPU_SOFTWARE_FP     FALSE
160
161/*
162 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
163 *
164 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
165 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
166 *
167 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
168 */
169
170#define CPU_ALL_TASKS_ARE_FP     FALSE
171
172/*
173 *  Should the IDLE task have a floating point context?
174 *
175 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
176 *  and it has a floating point context which is switched in and out.
177 *  If FALSE, then the IDLE task does not have a floating point context.
178 *
179 *  Setting this to TRUE negatively impacts the time required to preempt
180 *  the IDLE task from an interrupt because the floating point context
181 *  must be saved as part of the preemption.
182 */
183
184#define CPU_IDLE_TASK_IS_FP      FALSE
185
186/*
187 *  Should the saving of the floating point registers be deferred
188 *  until a context switch is made to another different floating point
189 *  task?
190 *
191 *  If TRUE, then the floating point context will not be stored until
192 *  necessary.  It will remain in the floating point registers and not
193 *  disturned until another floating point task is switched to.
194 *
195 *  If FALSE, then the floating point context is saved when a floating
196 *  point task is switched out and restored when the next floating point
197 *  task is restored.  The state of the floating point registers between
198 *  those two operations is not specified.
199 *
200 *  If the floating point context does NOT have to be saved as part of
201 *  interrupt dispatching, then it should be safe to set this to TRUE.
202 *
203 *  Setting this flag to TRUE results in using a different algorithm
204 *  for deciding when to save and restore the floating point context.
205 *  The deferred FP switch algorithm minimizes the number of times
206 *  the FP context is saved and restored.  The FP context is not saved
207 *  until a context switch is made to another, different FP task.
208 *  Thus in a system with only one FP task, the FP context will never
209 *  be saved or restored.
210 */
211
212#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
213
214/*
215 *  Does this port provide a CPU dependent IDLE task implementation?
216 *
217 *  If TRUE, then the routine _CPU_Thread_Idle_body
218 *  must be provided and is the default IDLE thread body instead of
219 *  _CPU_Thread_Idle_body.
220 *
221 *  If FALSE, then use the generic IDLE thread body if the BSP does
222 *  not provide one.
223 *
224 *  This is intended to allow for supporting processors which have
225 *  a low power or idle mode.  When the IDLE thread is executed, then
226 *  the CPU can be powered down.
227 *
228 *  The order of precedence for selecting the IDLE thread body is:
229 *
230 *    1.  BSP provided
231 *    2.  CPU dependent (if provided)
232 *    3.  generic (if no BSP and no CPU dependent)
233 */
234
235#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
236
237/*
238 *  Does the stack grow up (toward higher addresses) or down
239 *  (toward lower addresses)?
240 *
241 *  If TRUE, then the grows upward.
242 *  If FALSE, then the grows toward smaller addresses.
243 */
244
245#if defined(__hppa__)
246#define CPU_STACK_GROWS_UP               TRUE
247#elif defined(__sparc__) || defined(__i386__)
248#define CPU_STACK_GROWS_UP               FALSE
249#else
250#error "unknown CPU!!"
251#endif
252
253
254/*
255 *  The following is the variable attribute used to force alignment
256 *  of critical RTEMS structures.  On some processors it may make
257 *  sense to have these aligned on tighter boundaries than
258 *  the minimum requirements of the compiler in order to have as
259 *  much of the critical data area as possible in a cache line.
260 *
261 *  The placement of this macro in the declaration of the variables
262 *  is based on the syntactically requirements of the GNU C
263 *  "__attribute__" extension.  For example with GNU C, use
264 *  the following to force a structures to a 32 byte boundary.
265 *
266 *      __attribute__ ((aligned (32)))
267 *
268 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
269 *         To benefit from using this, the data must be heavily
270 *         used so it will stay in the cache and used frequently enough
271 *         in the executive to justify turning this on.
272 *
273 *  This is really not critical on the POSIX simulator ports as
274 *  performance is not the goal here.
275 */
276
277#define CPU_STRUCTURE_ALIGNMENT
278
279/*
280 *  Define what is required to specify how the network to host conversion
281 *  routines are handled.
282 */
283
284#if defined(__hppa__) || defined(__sparc__)
285#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
286#define CPU_BIG_ENDIAN                           TRUE
287#define CPU_LITTLE_ENDIAN                        FALSE
288#elif defined(__i386__)
289#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
290#define CPU_BIG_ENDIAN                           FALSE
291#define CPU_LITTLE_ENDIAN                        TRUE
292#else
293#error "Unknown CPU!!!"
294#endif
295
296/*
297 *  The following defines the number of bits actually used in the
298 *  interrupt field of the task mode.  How those bits map to the
299 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
300 */
301
302#define CPU_MODES_INTERRUPT_MASK   0x00000001
303
304#define CPU_NAME "UNIX"
305
306/*
307 *  Processor defined structures
308 *
309 *  Examples structures include the descriptor tables from the i386
310 *  and the processor control structure on the i960ca.
311 */
312
313/* may need to put some structures here.  */
314
315#if defined(__hppa__)
316/*
317 * Word indices within a jmp_buf structure
318 */
319
320#ifdef RTEMS_NEWLIB_SETJMP
321#define RP_OFF       6
322#define SP_OFF       2
323#define R3_OFF      10
324#define R4_OFF      11
325#define R5_OFF      12
326#define R6_OFF      13
327#define R7_OFF      14
328#define R8_OFF      15
329#define R9_OFF      16
330#define R10_OFF     17
331#define R11_OFF     18
332#define R12_OFF     19
333#define R13_OFF     20
334#define R14_OFF     21
335#define R15_OFF     22
336#define R16_OFF     23
337#define R17_OFF     24
338#define R18_OFF     25
339#define DP_OFF      26
340#endif
341
342#ifdef RTEMS_UNIXLIB_SETJMP
343#define RP_OFF       0
344#define SP_OFF       1
345#define R3_OFF       4
346#define R4_OFF       5
347#define R5_OFF       6
348#define R6_OFF       7
349#define R7_OFF       8
350#define R8_OFF       9
351#define R9_OFF      10
352#define R10_OFF     11
353#define R11_OFF     12
354#define R12_OFF     13
355#define R13_OFF     14
356#define R14_OFF     15
357#define R15_OFF     16
358#define R16_OFF     17
359#define R17_OFF     18
360#define R18_OFF     19
361#define DP_OFF      20
362#endif
363#endif
364
365#if defined(__i386__)
366 
367#ifdef RTEMS_NEWLIB
368#error "Newlib not installed"
369#endif
370 
371/*
372 *  For i386 targets
373 */
374 
375#ifdef RTEMS_UNIXLIB
376#if defined(__FreeBSD__)
377#define RET_OFF    0
378#define EBX_OFF    1
379#define EBP_OFF    2
380#define ESP_OFF    3
381#define ESI_OFF    4
382#define EDI_OFF    5
383#elif defined(__CYGWIN__)
384#define EAX_OFF    0
385#define EBX_OFF    1
386#define ECX_OFF    2
387#define EDX_OFF    3
388#define ESI_OFF    4
389#define EDI_OFF    5
390#define EBP_OFF    6
391#define ESP_OFF    7
392#define RET_OFF    8
393#else
394/* Linux */
395#define EBX_OFF    0
396#define ESI_OFF    1
397#define EDI_OFF    2
398#define EBP_OFF    3
399#define ESP_OFF    4
400#define RET_OFF    5
401#endif
402#endif
403 
404#endif
405 
406#if defined(__sparc__)
407
408/*
409 *  Word indices within a jmp_buf structure
410 */
411 
412#ifdef RTEMS_NEWLIB
413#define ADDR_ADJ_OFFSET -8
414#define SP_OFF    0
415#define RP_OFF    1
416#define FP_OFF    2
417#endif
418
419#ifdef RTEMS_UNIXLIB
420#define ADDR_ADJ_OFFSET 0
421#define G0_OFF    0
422#define SP_OFF    1
423#define RP_OFF    2   
424#define FP_OFF    3
425#define I7_OFF    4
426#endif
427
428#endif
429
430/*
431 * Contexts
432 *
433 *  Generally there are 2 types of context to save.
434 *     1. Interrupt registers to save
435 *     2. Task level registers to save
436 *
437 *  This means we have the following 3 context items:
438 *     1. task level context stuff::  Context_Control
439 *     2. floating point task stuff:: Context_Control_fp
440 *     3. special interrupt level context :: Context_Control_interrupt
441 *
442 *  On some processors, it is cost-effective to save only the callee
443 *  preserved registers during a task context switch.  This means
444 *  that the ISR code needs to save those registers which do not
445 *  persist across function calls.  It is not mandatory to make this
446 *  distinctions between the caller/callee saves registers for the
447 *  purpose of minimizing context saved during task switch and on interrupts.
448 *  If the cost of saving extra registers is minimal, simplicity is the
449 *  choice.  Save the same context on interrupt entry as for tasks in
450 *  this case.
451 *
452 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
453 *  care should be used in designing the context area.
454 *
455 *  On some CPUs with hardware floating point support, the Context_Control_fp
456 *  structure will not be used or it simply consist of an array of a
457 *  fixed number of bytes.   This is done when the floating point context
458 *  is dumped by a "FP save context" type instruction and the format
459 *  is not really defined by the CPU.  In this case, there is no need
460 *  to figure out the exact format -- only the size.  Of course, although
461 *  this is enough information for RTEMS, it is probably not enough for
462 *  a debugger such as gdb.  But that is another problem.
463 */
464
465/*
466 *  This is really just the area for the following fields.
467 *
468 *    jmp_buf    regs;
469 *    uint32_t   isr_level;
470 *
471 *  Doing it this way avoids conflicts between the native stuff and the
472 *  RTEMS stuff.
473 *
474 *  NOTE:
475 *      hpux9 setjmp is optimized for the case where the setjmp buffer
476 *      is 8 byte aligned.  In a RISC world, this seems likely to enable
477 *      8 byte copies, especially for the float registers.
478 *      So we always align them on 8 byte boundaries.
479 */
480
481#ifdef __GNUC__
482#define CONTEXT_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (8)))
483#else
484#define CONTEXT_STRUCTURE_ALIGNMENT
485#endif
486
487typedef struct {
488  char      Area[ SIZEOF_CPU_CONTEXT ] CONTEXT_STRUCTURE_ALIGNMENT;
489} Context_Control;
490
491typedef struct {
492} Context_Control_fp;
493
494typedef struct {
495} CPU_Interrupt_frame;
496
497
498/*
499 *  The following table contains the information required to configure
500 *  the UNIX Simulator specific parameters.
501 */
502
503typedef struct {
504  void       (*pretasking_hook)( void );
505  void       (*predriver_hook)( void );
506  void       (*postdriver_hook)( void );
507  void       (*idle_task)( void );
508  boolean      do_zero_of_workspace;
509  uint32_t     idle_task_stack_size;
510  uint32_t     interrupt_stack_size;
511  uint32_t     extra_mpci_receive_server_stack;
512  void *     (*stack_allocate_hook)( uint32_t   );
513  void       (*stack_free_hook)( void* );
514  /* end of required fields */
515}   rtems_cpu_table;
516
517/*
518 *  Macros to access required entires in the CPU Table are in
519 *  the file rtems/system.h.
520 */
521
522/*
523 *  Macros to access UNIX specific additions to the CPU Table
524 */
525
526/* There are no CPU specific additions to the CPU Table for this port. */
527
528/*
529 *  This variable is optional.  It is used on CPUs on which it is difficult
530 *  to generate an "uninitialized" FP context.  It is filled in by
531 *  _CPU_Initialize and copied into the task's FP context area during
532 *  _CPU_Context_Initialize.
533 */
534
535SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
536
537/*
538 *  On some CPUs, RTEMS supports a software managed interrupt stack.
539 *  This stack is allocated by the Interrupt Manager and the switch
540 *  is performed in _ISR_Handler.  These variables contain pointers
541 *  to the lowest and highest addresses in the chunk of memory allocated
542 *  for the interrupt stack.  Since it is unknown whether the stack
543 *  grows up or down (in general), this give the CPU dependent
544 *  code the option of picking the version it wants to use.
545 *
546 *  NOTE: These two variables are required if the macro
547 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
548 */
549
550SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
551SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
552
553/*
554 *  With some compilation systems, it is difficult if not impossible to
555 *  call a high-level language routine from assembly language.  This
556 *  is especially true of commercial Ada compilers and name mangling
557 *  C++ ones.  This variable can be optionally defined by the CPU porter
558 *  and contains the address of the routine _Thread_Dispatch.  This
559 *  can make it easier to invoke that routine at the end of the interrupt
560 *  sequence (if a dispatch is necessary).
561 */
562
563SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
564
565/*
566 *  Nothing prevents the porter from declaring more CPU specific variables.
567 */
568
569/* XXX: if needed, put more variables here */
570
571/*
572 *  The size of the floating point context area.  On some CPUs this
573 *  will not be a "sizeof" because the format of the floating point
574 *  area is not defined -- only the size is.  This is usually on
575 *  CPUs with a "floating point save context" instruction.
576 */
577
578#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
579
580/*
581 * The size of a frame on the stack
582 */
583
584#if defined(__hppa__)
585#define CPU_FRAME_SIZE  (32 * 4)
586#elif defined(__sparc__)
587#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
588#elif defined(__i386__)
589#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
590#else
591#error "Unknown CPU!!!"
592#endif
593
594/*
595 *  Amount of extra stack (above minimum stack size) required by
596 *  MPCI receive server thread.  Remember that in a multiprocessor
597 *  system this thread must exist and be able to process all directives.
598 */
599
600#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
601
602/*
603 *  This defines the number of entries in the ISR_Vector_table managed
604 *  by RTEMS.
605 */
606
607#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
608#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
609
610/*
611 *  This is defined if the port has a special way to report the ISR nesting
612 *  level.  Most ports maintain the variable _ISR_Nest_level.
613 */
614
615#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
616
617/*
618 *  Should be large enough to run all RTEMS tests.  This insures
619 *  that a "reasonable" small application should not have any problems.
620 */
621
622#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
623
624/*
625 *  CPU's worst alignment requirement for data types on a byte boundary.  This
626 *  alignment does not take into account the requirements for the stack.
627 */
628
629#define CPU_ALIGNMENT              8
630
631/*
632 *  This number corresponds to the byte alignment requirement for the
633 *  heap handler.  This alignment requirement may be stricter than that
634 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
635 *  common for the heap to follow the same alignment requirement as
636 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
637 *  then this should be set to CPU_ALIGNMENT.
638 *
639 *  NOTE:  This does not have to be a power of 2.  It does have to
640 *         be greater or equal to than CPU_ALIGNMENT.
641 */
642
643#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
644
645/*
646 *  This number corresponds to the byte alignment requirement for memory
647 *  buffers allocated by the partition manager.  This alignment requirement
648 *  may be stricter than that for the data types alignment specified by
649 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
650 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
651 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
652 *
653 *  NOTE:  This does not have to be a power of 2.  It does have to
654 *         be greater or equal to than CPU_ALIGNMENT.
655 */
656
657#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
658
659/*
660 *  This number corresponds to the byte alignment requirement for the
661 *  stack.  This alignment requirement may be stricter than that for the
662 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
663 *  is strict enough for the stack, then this should be set to 0.
664 *
665 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
666 */
667
668#define CPU_STACK_ALIGNMENT        64
669
670/*
671 *  ISR handler macros
672 */
673
674/*
675 *  Support routine to initialize the RTEMS vector table after it is allocated.
676 */
677
678void _CPU_Initialize_vectors(void);
679
680/*
681 *  Disable all interrupts for an RTEMS critical section.  The previous
682 *  level is returned in _level.
683 */
684
685extern uint32_t   _CPU_ISR_Disable_support(void);
686
687#define _CPU_ISR_Disable( _level ) \
688    do { \
689      (_level) = _CPU_ISR_Disable_support(); \
690    } while ( 0 )
691
692/*
693 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
694 *  This indicates the end of an RTEMS critical section.  The parameter
695 *  _level is not modified.
696 */
697
698void _CPU_ISR_Enable(uint32_t   level);
699
700/*
701 *  This temporarily restores the interrupt to _level before immediately
702 *  disabling them again.  This is used to divide long RTEMS critical
703 *  sections into two or more parts.  The parameter _level is not
704 * modified.
705 */
706
707#define _CPU_ISR_Flash( _level ) \
708  do { \
709      register uint32_t   _ignored = 0; \
710      _CPU_ISR_Enable( (_level) ); \
711      _CPU_ISR_Disable( _ignored ); \
712  } while ( 0 )
713
714/*
715 *  Map interrupt level in task mode onto the hardware that the CPU
716 *  actually provides.  Currently, interrupt levels which do not
717 *  map onto the CPU in a generic fashion are undefined.  Someday,
718 *  it would be nice if these were "mapped" by the application
719 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
720 *  8 - 255 would be available for bsp/application specific meaning.
721 *  This could be used to manage a programmable interrupt controller
722 *  via the rtems_task_mode directive.
723 */
724
725#define _CPU_ISR_Set_level( new_level ) \
726  { \
727    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
728    else                  _CPU_ISR_Enable( 1 ); \
729  }
730
731uint32_t   _CPU_ISR_Get_level( void );
732
733/* end of ISR handler macros */
734
735/* Context handler macros */
736
737/*
738 *  This routine is responsible for somehow restarting the currently
739 *  executing task.  If you are lucky, then all that is necessary
740 *  is restoring the context.  Otherwise, there will need to be
741 *  a special assembly routine which does something special in this
742 *  case.  Context_Restore should work most of the time.  It will
743 *  not work if restarting self conflicts with the stack frame
744 *  assumptions of restoring a context.
745 */
746
747#define _CPU_Context_Restart_self( _the_context ) \
748   _CPU_Context_restore( (_the_context) );
749
750/*
751 *  The purpose of this macro is to allow the initial pointer into
752 *  a floating point context area (used to save the floating point
753 *  context) to be at an arbitrary place in the floating point
754 *  context area.
755 *
756 *  This is necessary because some FP units are designed to have
757 *  their context saved as a stack which grows into lower addresses.
758 *  Other FP units can be saved by simply moving registers into offsets
759 *  from the base of the context area.  Finally some FP units provide
760 *  a "dump context" instruction which could fill in from high to low
761 *  or low to high based on the whim of the CPU designers.
762 */
763
764#define _CPU_Context_Fp_start( _base, _offset ) \
765   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
766
767/*
768 *  This routine initializes the FP context area passed to it to.
769 *  There are a few standard ways in which to initialize the
770 *  floating point context.  The code included for this macro assumes
771 *  that this is a CPU in which a "initial" FP context was saved into
772 *  _CPU_Null_fp_context and it simply copies it to the destination
773 *  context passed to it.
774 *
775 *  Other models include (1) not doing anything, and (2) putting
776 *  a "null FP status word" in the correct place in the FP context.
777 */
778
779#define _CPU_Context_Initialize_fp( _destination ) \
780  { \
781   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
782  }
783
784#define _CPU_Context_save_fp( _fp_context ) \
785    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
786
787#define _CPU_Context_restore_fp( _fp_context ) \
788    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
789
790extern void _CPU_Context_Initialize(
791  Context_Control  *_the_context,
792  uint32_t         *_stack_base,
793  uint32_t          _size,
794  uint32_t          _new_level,
795  void             *_entry_point,
796  boolean           _is_fp
797);
798
799/* end of Context handler macros */
800
801/* Fatal Error manager macros */
802
803/*
804 *  This routine copies _error into a known place -- typically a stack
805 *  location or a register, optionally disables interrupts, and
806 *  halts/stops the CPU.
807 */
808
809#define _CPU_Fatal_halt( _error ) \
810    _CPU_Fatal_error( _error )
811
812/* end of Fatal Error manager macros */
813
814/* Bitfield handler macros */
815
816/*
817 *  This routine sets _output to the bit number of the first bit
818 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
819 *  This type may be either 16 or 32 bits wide although only the 16
820 *  least significant bits will be used.
821 *
822 *  There are a number of variables in using a "find first bit" type
823 *  instruction.
824 *
825 *    (1) What happens when run on a value of zero?
826 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
827 *    (3) The numbering may be zero or one based.
828 *    (4) The "find first bit" instruction may search from MSB or LSB.
829 *
830 *  RTEMS guarantees that (1) will never happen so it is not a concern.
831 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
832 *  _CPU_Priority_bits_index().  These three form a set of routines
833 *  which must logically operate together.  Bits in the _value are
834 *  set and cleared based on masks built by _CPU_Priority_mask().
835 *  The basic major and minor values calculated by _Priority_Major()
836 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
837 *  to properly range between the values returned by the "find first bit"
838 *  instruction.  This makes it possible for _Priority_Get_highest() to
839 *  calculate the major and directly index into the minor table.
840 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
841 *  is the first bit found.
842 *
843 *  This entire "find first bit" and mapping process depends heavily
844 *  on the manner in which a priority is broken into a major and minor
845 *  components with the major being the 4 MSB of a priority and minor
846 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
847 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
848 *  to the lowest priority.
849 *
850 *  If your CPU does not have a "find first bit" instruction, then
851 *  there are ways to make do without it.  Here are a handful of ways
852 *  to implement this in software:
853 *
854 *    - a series of 16 bit test instructions
855 *    - a "binary search using if's"
856 *    - _number = 0
857 *      if _value > 0x00ff
858 *        _value >>=8
859 *        _number = 8;
860 *
861 *      if _value > 0x0000f
862 *        _value >=8
863 *        _number += 4
864 *
865 *      _number += bit_set_table[ _value ]
866 *
867 *    where bit_set_table[ 16 ] has values which indicate the first
868 *      bit set
869 */
870
871/*
872 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
873 *  dependencies on either a native bitscan instruction or an ffs() in the
874 *  C library.
875 */
876 
877#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
878#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
879 
880/* end of Bitfield handler macros */
881 
882/* Priority handler handler macros */
883 
884/*
885 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
886 *  dependencies on either a native bitscan instruction or an ffs() in the
887 *  C library.
888 */
889 
890/* end of Priority handler macros */
891
892/* functions */
893
894/*
895 *  _CPU_Initialize
896 *
897 *  This routine performs CPU dependent initialization.
898 */
899
900void _CPU_Initialize(
901  rtems_cpu_table  *cpu_table,
902  void      (*thread_dispatch)
903);
904
905/*
906 *  _CPU_ISR_install_raw_handler
907 *
908 *  This routine installs a "raw" interrupt handler directly into the
909 *  processor's vector table.
910 */
911 
912void _CPU_ISR_install_raw_handler(
913  uint32_t    vector,
914  proc_ptr    new_handler,
915  proc_ptr   *old_handler
916);
917
918/*
919 *  _CPU_ISR_install_vector
920 *
921 *  This routine installs an interrupt vector.
922 */
923
924void _CPU_ISR_install_vector(
925  uint32_t    vector,
926  proc_ptr    new_handler,
927  proc_ptr   *old_handler
928);
929
930/*
931 *  _CPU_Install_interrupt_stack
932 *
933 *  This routine installs the hardware interrupt stack pointer.
934 *
935 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
936 *         is TRUE.
937 */
938
939void _CPU_Install_interrupt_stack( void );
940
941/*
942 *  _CPU_Thread_Idle_body
943 *
944 *  This routine is the CPU dependent IDLE thread body.
945 *
946 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
947 *         is TRUE.
948 */
949
950void _CPU_Thread_Idle_body( void );
951
952/*
953 *  _CPU_Context_switch
954 *
955 *  This routine switches from the run context to the heir context.
956 */
957
958void _CPU_Context_switch(
959  Context_Control  *run,
960  Context_Control  *heir
961);
962
963/*
964 *  _CPU_Context_restore
965 *
966 *  This routine is generally used only to restart self in an
967 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
968 *
969 *  NOTE: May be unnecessary to reload some registers.
970 */
971
972void _CPU_Context_restore(
973  Context_Control *new_context
974);
975
976/*
977 *  _CPU_Save_float_context
978 *
979 *  This routine saves the floating point context passed to it.
980 */
981
982void _CPU_Save_float_context(
983  Context_Control_fp *fp_context_ptr
984);
985
986/*
987 *  _CPU_Restore_float_context
988 *
989 *  This routine restores the floating point context passed to it.
990 */
991
992void _CPU_Restore_float_context(
993  Context_Control_fp *fp_context_ptr
994);
995
996
997void _CPU_ISR_Set_signal_level(
998  uint32_t   level
999);
1000
1001void _CPU_Fatal_error(
1002  uint32_t   _error
1003);
1004
1005/*  The following routine swaps the endian format of an unsigned int.
1006 *  It must be static because it is referenced indirectly.
1007 *
1008 *  This version will work on any processor, but if there is a better
1009 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1010 *
1011 *     swap least significant two bytes with 16-bit rotate
1012 *     swap upper and lower 16-bits
1013 *     swap most significant two bytes with 16-bit rotate
1014 *
1015 *  Some CPUs have special instructions which swap a 32-bit quantity in
1016 *  a single instruction (e.g. i486).  It is probably best to avoid
1017 *  an "endian swapping control bit" in the CPU.  One good reason is
1018 *  that interrupts would probably have to be disabled to insure that
1019 *  an interrupt does not try to access the same "chunk" with the wrong
1020 *  endian.  Another good reason is that on some CPUs, the endian bit
1021 *  endianness for ALL fetches -- both code and data -- so the code
1022 *  will be fetched incorrectly.
1023 */
1024 
1025static inline unsigned int CPU_swap_u32(
1026  unsigned int value
1027)
1028{
1029  uint32_t   byte1, byte2, byte3, byte4, swapped;
1030 
1031  byte4 = (value >> 24) & 0xff;
1032  byte3 = (value >> 16) & 0xff;
1033  byte2 = (value >> 8)  & 0xff;
1034  byte1 =  value        & 0xff;
1035 
1036  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1037  return( swapped );
1038}
1039
1040#define CPU_swap_u16( value ) \
1041  (((value&0xff) << 8) | ((value >> 8)&0xff))
1042
1043/*
1044 *  Special Purpose Routines to hide the use of UNIX system calls.
1045 */
1046
1047
1048/*
1049 *  Pointer to a sync io  Handler
1050 */
1051
1052typedef void ( *rtems_sync_io_handler )(
1053  int fd,
1054  boolean read,
1055  boolean wrtie,
1056  boolean except
1057);
1058
1059/* returns -1 if fd to large, 0 is successful */
1060int _CPU_Set_sync_io_handler(
1061  int fd,
1062  boolean read,
1063  boolean write,
1064  boolean except,
1065  rtems_sync_io_handler handler
1066);
1067
1068/* returns -1 if fd to large, o if successful */
1069int _CPU_Clear_sync_io_handler(
1070  int fd
1071);
1072
1073int _CPU_Get_clock_vector( void );
1074
1075void _CPU_Start_clock( 
1076  int microseconds
1077);
1078
1079void _CPU_Stop_clock( void );
1080
1081#if defined(RTEMS_MULTIPROCESSING)
1082
1083void _CPU_SHM_Init( 
1084  uint32_t     maximum_nodes,
1085  boolean      is_master_node,
1086  void       **shm_address,
1087  uint32_t    *shm_length
1088);
1089
1090int _CPU_Get_pid( void );
1091 
1092int _CPU_SHM_Get_vector( void );
1093 
1094void _CPU_SHM_Send_interrupt(
1095  int pid,
1096  int vector
1097);
1098 
1099void _CPU_SHM_Lock( 
1100  int semaphore
1101);
1102
1103void _CPU_SHM_Unlock(
1104  int semaphore
1105);
1106#endif
1107
1108#ifdef __cplusplus
1109}
1110#endif
1111
1112#endif
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