source: rtems/cpukit/score/cpu/unix/rtems/score/cpu.h @ c094542

4.104.114.84.95
Last change on this file since c094542 was c094542, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 16, 1999 at 4:07:17 PM

Only check for System V IPC if multiprocessing is enabled. The unix
port only uses System V IPC for shared memory and semaphores to
communicate between nodes in a multiprocessor configuration. If you
disable multiprocessing, then this code should be unused. Thus systems
like Cygwin which are POSIX but do not support System V IPC should
not work.

  • Property mode set to 100644
File size: 32.0 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the HP
4 *  PA-RISC processor (Level 1.1).
5 *
6 *  COPYRIGHT (c) 1994 by Division Incorporated
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  $Id$
13 */
14
15#ifndef __CPU_h
16#define __CPU_h
17
18#ifdef __cplusplus
19extern "C" {
20#endif
21
22#include <rtems/score/unix.h>              /* pick up machine definitions */
23#ifndef ASM
24#include <rtems/score/unixtypes.h>
25#endif
26
27#include <rtems/score/unixsize.h>
28
29#if defined(solaris2)
30#undef  _POSIX_C_SOURCE
31#define _POSIX_C_SOURCE 3
32#undef  __STRICT_ANSI__
33#define __STRICT_ANSI__
34#endif
35
36#if defined(linux)
37#define MALLOC_0_RETURNS_NULL
38#endif
39
40/* conditional compilation parameters */
41
42/*
43 *  Should the calls to _Thread_Enable_dispatch be inlined?
44 *
45 *  If TRUE, then they are inlined.
46 *  If FALSE, then a subroutine call is made.
47 *
48 *  Basically this is an example of the classic trade-off of size
49 *  versus speed.  Inlining the call (TRUE) typically increases the
50 *  size of RTEMS while speeding up the enabling of dispatching.
51 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
52 *  only be 0 or 1 unless you are in an interrupt handler and that
53 *  interrupt handler invokes the executive.]  When not inlined
54 *  something calls _Thread_Enable_dispatch which in turns calls
55 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
56 *  one subroutine call is avoided entirely.]
57 */
58
59#define CPU_INLINE_ENABLE_DISPATCH       FALSE
60
61/*
62 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
63 *  be unrolled one time?  In unrolled each iteration of the loop examines
64 *  two "nodes" on the chain being searched.  Otherwise, only one node
65 *  is examined per iteration.
66 *
67 *  If TRUE, then the loops are unrolled.
68 *  If FALSE, then the loops are not unrolled.
69 *
70 *  The primary factor in making this decision is the cost of disabling
71 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
72 *  body of the loop.  On some CPUs, the flash is more expensive than
73 *  one iteration of the loop body.  In this case, it might be desirable
74 *  to unroll the loop.  It is important to note that on some CPUs, this
75 *  code is the longest interrupt disable period in RTEMS.  So it is
76 *  necessary to strike a balance when setting this parameter.
77 */
78
79#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
80
81/*
82 *  Does RTEMS manage a dedicated interrupt stack in software?
83 *
84 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
85 *  If FALSE, nothing is done.
86 *
87 *  If the CPU supports a dedicated interrupt stack in hardware,
88 *  then it is generally the responsibility of the BSP to allocate it
89 *  and set it up.
90 *
91 *  If the CPU does not support a dedicated interrupt stack, then
92 *  the porter has two options: (1) execute interrupts on the
93 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
94 *  interrupt stack.
95 *
96 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
97 *
98 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
99 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
100 *  possible that both are FALSE for a particular CPU.  Although it
101 *  is unclear what that would imply about the interrupt processing
102 *  procedure on that CPU.
103 */
104
105#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
106
107/*
108 *  Does this CPU have hardware support for a dedicated interrupt stack?
109 *
110 *  If TRUE, then it must be installed during initialization.
111 *  If FALSE, then no installation is performed.
112 *
113 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
114 *
115 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
116 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
117 *  possible that both are FALSE for a particular CPU.  Although it
118 *  is unclear what that would imply about the interrupt processing
119 *  procedure on that CPU.
120 */
121
122#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
123
124/*
125 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
126 *
127 *  If TRUE, then the memory is allocated during initialization.
128 *  If FALSE, then the memory is allocated during initialization.
129 *
130 *  This should be TRUE if CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
131 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
132 */
133
134#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
135
136/*
137 *  Does the RTEMS invoke the user's ISR with the vector number and
138 *  a pointer to the saved interrupt frame (1) or just the vector
139 *  number (0)?
140 */
141
142#define CPU_ISR_PASSES_FRAME_POINTER 0
143
144/*
145 *  Does the CPU have hardware floating point?
146 *
147 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
148 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
149 *
150 *  If there is a FP coprocessor such as the i387 or mc68881, then
151 *  the answer is TRUE.
152 *
153 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
154 *  It indicates whether or not this CPU model has FP support.  For
155 *  example, it would be possible to have an i386_nofp CPU model
156 *  which set this to false to indicate that you have an i386 without
157 *  an i387 and wish to leave floating point support out of RTEMS.
158 */
159
160#define CPU_HARDWARE_FP     TRUE
161
162/*
163 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
164 *
165 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
166 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
167 *
168 *  So far, the only CPU in which this option has been used is the
169 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
170 *  floating point registers to perform integer multiplies.  If
171 *  a function which you would not think utilize the FP unit DOES,
172 *  then one can not easily predict which tasks will use the FP hardware.
173 *  In this case, this option should be TRUE.
174 *
175 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
176 */
177
178#define CPU_ALL_TASKS_ARE_FP     FALSE
179
180/*
181 *  Should the IDLE task have a floating point context?
182 *
183 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
184 *  and it has a floating point context which is switched in and out.
185 *  If FALSE, then the IDLE task does not have a floating point context.
186 *
187 *  Setting this to TRUE negatively impacts the time required to preempt
188 *  the IDLE task from an interrupt because the floating point context
189 *  must be saved as part of the preemption.
190 */
191
192#define CPU_IDLE_TASK_IS_FP      FALSE
193
194/*
195 *  Should the saving of the floating point registers be deferred
196 *  until a context switch is made to another different floating point
197 *  task?
198 *
199 *  If TRUE, then the floating point context will not be stored until
200 *  necessary.  It will remain in the floating point registers and not
201 *  disturned until another floating point task is switched to.
202 *
203 *  If FALSE, then the floating point context is saved when a floating
204 *  point task is switched out and restored when the next floating point
205 *  task is restored.  The state of the floating point registers between
206 *  those two operations is not specified.
207 *
208 *  If the floating point context does NOT have to be saved as part of
209 *  interrupt dispatching, then it should be safe to set this to TRUE.
210 *
211 *  Setting this flag to TRUE results in using a different algorithm
212 *  for deciding when to save and restore the floating point context.
213 *  The deferred FP switch algorithm minimizes the number of times
214 *  the FP context is saved and restored.  The FP context is not saved
215 *  until a context switch is made to another, different FP task.
216 *  Thus in a system with only one FP task, the FP context will never
217 *  be saved or restored.
218 */
219
220#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
221
222/*
223 *  Does this port provide a CPU dependent IDLE task implementation?
224 *
225 *  If TRUE, then the routine _CPU_Thread_Idle_body
226 *  must be provided and is the default IDLE thread body instead of
227 *  _CPU_Thread_Idle_body.
228 *
229 *  If FALSE, then use the generic IDLE thread body if the BSP does
230 *  not provide one.
231 *
232 *  This is intended to allow for supporting processors which have
233 *  a low power or idle mode.  When the IDLE thread is executed, then
234 *  the CPU can be powered down.
235 *
236 *  The order of precedence for selecting the IDLE thread body is:
237 *
238 *    1.  BSP provided
239 *    2.  CPU dependent (if provided)
240 *    3.  generic (if no BSP and no CPU dependent)
241 */
242
243#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
244
245/*
246 *  Does the stack grow up (toward higher addresses) or down
247 *  (toward lower addresses)?
248 *
249 *  If TRUE, then the grows upward.
250 *  If FALSE, then the grows toward smaller addresses.
251 */
252
253#if defined(__hppa__)
254#define CPU_STACK_GROWS_UP               TRUE
255#elif defined(__sparc__) || defined(__i386__)
256#define CPU_STACK_GROWS_UP               FALSE
257#else
258#error "unknown CPU!!"
259#endif
260
261
262/*
263 *  The following is the variable attribute used to force alignment
264 *  of critical RTEMS structures.  On some processors it may make
265 *  sense to have these aligned on tighter boundaries than
266 *  the minimum requirements of the compiler in order to have as
267 *  much of the critical data area as possible in a cache line.
268 *
269 *  The placement of this macro in the declaration of the variables
270 *  is based on the syntactically requirements of the GNU C
271 *  "__attribute__" extension.  For example with GNU C, use
272 *  the following to force a structures to a 32 byte boundary.
273 *
274 *      __attribute__ ((aligned (32)))
275 *
276 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
277 *         To benefit from using this, the data must be heavily
278 *         used so it will stay in the cache and used frequently enough
279 *         in the executive to justify turning this on.
280 */
281
282#ifdef __GNUC__
283#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (32)))
284#else
285#define CPU_STRUCTURE_ALIGNMENT
286#endif
287
288/*
289 *  Define what is required to specify how the network to host conversion
290 *  routines are handled.
291 */
292
293#if defined(__hppa__) || defined(__sparc__)
294#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
295#define CPU_BIG_ENDIAN                           TRUE
296#define CPU_LITTLE_ENDIAN                        FALSE
297#elif defined(__i386__)
298#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
299#define CPU_BIG_ENDIAN                           FALSE
300#define CPU_LITTLE_ENDIAN                        TRUE
301#else
302#error "Unknown CPU!!!"
303#endif
304
305/*
306 *  The following defines the number of bits actually used in the
307 *  interrupt field of the task mode.  How those bits map to the
308 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
309 */
310
311#define CPU_MODES_INTERRUPT_MASK   0x00000001
312
313#define CPU_NAME "UNIX"
314
315/*
316 *  Processor defined structures
317 *
318 *  Examples structures include the descriptor tables from the i386
319 *  and the processor control structure on the i960ca.
320 */
321
322/* may need to put some structures here.  */
323
324#if defined(__hppa__)
325/*
326 * Word indices within a jmp_buf structure
327 */
328
329#ifdef RTEMS_NEWLIB_SETJMP
330#define RP_OFF       6
331#define SP_OFF       2
332#define R3_OFF      10
333#define R4_OFF      11
334#define R5_OFF      12
335#define R6_OFF      13
336#define R7_OFF      14
337#define R8_OFF      15
338#define R9_OFF      16
339#define R10_OFF     17
340#define R11_OFF     18
341#define R12_OFF     19
342#define R13_OFF     20
343#define R14_OFF     21
344#define R15_OFF     22
345#define R16_OFF     23
346#define R17_OFF     24
347#define R18_OFF     25
348#define DP_OFF      26
349#endif
350
351#ifdef RTEMS_UNIXLIB_SETJMP
352#define RP_OFF       0
353#define SP_OFF       1
354#define R3_OFF       4
355#define R4_OFF       5
356#define R5_OFF       6
357#define R6_OFF       7
358#define R7_OFF       8
359#define R8_OFF       9
360#define R9_OFF      10
361#define R10_OFF     11
362#define R11_OFF     12
363#define R12_OFF     13
364#define R13_OFF     14
365#define R14_OFF     15
366#define R15_OFF     16
367#define R16_OFF     17
368#define R17_OFF     18
369#define R18_OFF     19
370#define DP_OFF      20
371#endif
372#endif
373
374#if defined(__i386__)
375 
376#ifdef RTEMS_NEWLIB
377#error "Newlib not installed"
378#endif
379 
380/*
381 *  For Linux 1.1
382 */
383 
384#ifdef RTEMS_UNIXLIB
385#if defined(__FreeBSD__)
386#define RET_OFF    0
387#define EBX_OFF    1
388#define EBP_OFF    2
389#define ESP_OFF    3
390#define ESI_OFF    4
391#define EDI_OFF    5
392#else
393#define EBX_OFF    0
394#define ESI_OFF    1
395#define EDI_OFF    2
396#define EBP_OFF    3
397#define ESP_OFF    4
398#define RET_OFF    5
399#endif
400#endif
401 
402#endif
403 
404#if defined(__sparc__)
405
406/*
407 *  Word indices within a jmp_buf structure
408 */
409 
410#ifdef RTEMS_NEWLIB
411#define ADDR_ADJ_OFFSET -8
412#define SP_OFF    0
413#define RP_OFF    1
414#define FP_OFF    2
415#endif
416
417#ifdef RTEMS_UNIXLIB
418#define ADDR_ADJ_OFFSET 0
419#define G0_OFF    0
420#define SP_OFF    1
421#define RP_OFF    2   
422#define FP_OFF    3
423#define I7_OFF    4
424#endif
425
426#endif
427
428/*
429 * Contexts
430 *
431 *  Generally there are 2 types of context to save.
432 *     1. Interrupt registers to save
433 *     2. Task level registers to save
434 *
435 *  This means we have the following 3 context items:
436 *     1. task level context stuff::  Context_Control
437 *     2. floating point task stuff:: Context_Control_fp
438 *     3. special interrupt level context :: Context_Control_interrupt
439 *
440 *  On some processors, it is cost-effective to save only the callee
441 *  preserved registers during a task context switch.  This means
442 *  that the ISR code needs to save those registers which do not
443 *  persist across function calls.  It is not mandatory to make this
444 *  distinctions between the caller/callee saves registers for the
445 *  purpose of minimizing context saved during task switch and on interrupts.
446 *  If the cost of saving extra registers is minimal, simplicity is the
447 *  choice.  Save the same context on interrupt entry as for tasks in
448 *  this case.
449 *
450 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
451 *  care should be used in designing the context area.
452 *
453 *  On some CPUs with hardware floating point support, the Context_Control_fp
454 *  structure will not be used or it simply consist of an array of a
455 *  fixed number of bytes.   This is done when the floating point context
456 *  is dumped by a "FP save context" type instruction and the format
457 *  is not really defined by the CPU.  In this case, there is no need
458 *  to figure out the exact format -- only the size.  Of course, although
459 *  this is enough information for RTEMS, it is probably not enough for
460 *  a debugger such as gdb.  But that is another problem.
461 */
462
463/*
464 *  This is really just the area for the following fields.
465 *
466 *    jmp_buf    regs;
467 *    unsigned32 isr_level;
468 *
469 *  Doing it this way avoids conflicts between the native stuff and the
470 *  RTEMS stuff.
471 *
472 *  NOTE:
473 *      hpux9 setjmp is optimized for the case where the setjmp buffer
474 *      is 8 byte aligned.  In a RISC world, this seems likely to enable
475 *      8 byte copies, especially for the float registers.
476 *      So we always align them on 8 byte boundaries.
477 */
478
479#ifdef __GNUC__
480#define CONTEXT_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (8)))
481#else
482#define CONTEXT_STRUCTURE_ALIGNMENT
483#endif
484
485typedef struct {
486  char      Area[ CPU_CONTEXT_SIZE_IN_BYTES ] CONTEXT_STRUCTURE_ALIGNMENT;
487} Context_Control;
488
489typedef struct {
490} Context_Control_fp;
491
492typedef struct {
493} CPU_Interrupt_frame;
494
495
496/*
497 *  The following table contains the information required to configure
498 *  the UNIX Simulator specific parameters.
499 */
500
501typedef struct {
502  void       (*pretasking_hook)( void );
503  void       (*predriver_hook)( void );
504  void       (*postdriver_hook)( void );
505  void       (*idle_task)( void );
506  boolean      do_zero_of_workspace;
507  unsigned32   idle_task_stack_size;
508  unsigned32   interrupt_stack_size;
509  unsigned32   extra_mpci_receive_server_stack;
510  void *     (*stack_allocate_hook)( unsigned32 );
511  void       (*stack_free_hook)( void* );
512  /* end of required fields */
513}   rtems_cpu_table;
514
515/*
516 *  Macros to access required entires in the CPU Table are in
517 *  the file rtems/system.h.
518 */
519
520/*
521 *  Macros to access UNIX specific additions to the CPU Table
522 */
523
524/* There are no CPU specific additions to the CPU Table for this port. */
525
526/*
527 *  This variable is optional.  It is used on CPUs on which it is difficult
528 *  to generate an "uninitialized" FP context.  It is filled in by
529 *  _CPU_Initialize and copied into the task's FP context area during
530 *  _CPU_Context_Initialize.
531 */
532
533SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
534
535/*
536 *  On some CPUs, RTEMS supports a software managed interrupt stack.
537 *  This stack is allocated by the Interrupt Manager and the switch
538 *  is performed in _ISR_Handler.  These variables contain pointers
539 *  to the lowest and highest addresses in the chunk of memory allocated
540 *  for the interrupt stack.  Since it is unknown whether the stack
541 *  grows up or down (in general), this give the CPU dependent
542 *  code the option of picking the version it wants to use.
543 *
544 *  NOTE: These two variables are required if the macro
545 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
546 */
547
548SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
549SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
550
551/*
552 *  With some compilation systems, it is difficult if not impossible to
553 *  call a high-level language routine from assembly language.  This
554 *  is especially true of commercial Ada compilers and name mangling
555 *  C++ ones.  This variable can be optionally defined by the CPU porter
556 *  and contains the address of the routine _Thread_Dispatch.  This
557 *  can make it easier to invoke that routine at the end of the interrupt
558 *  sequence (if a dispatch is necessary).
559 */
560
561SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
562
563/*
564 *  Nothing prevents the porter from declaring more CPU specific variables.
565 */
566
567/* XXX: if needed, put more variables here */
568
569/*
570 *  The size of the floating point context area.  On some CPUs this
571 *  will not be a "sizeof" because the format of the floating point
572 *  area is not defined -- only the size is.  This is usually on
573 *  CPUs with a "floating point save context" instruction.
574 */
575
576#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
577
578/*
579 * The size of a frame on the stack
580 */
581
582#if defined(__hppa__)
583#define CPU_FRAME_SIZE  (32 * 4)
584#elif defined(__sparc__)
585#define CPU_FRAME_SIZE  (112)   /* based on disassembled test code */
586#elif defined(__i386__)
587#define CPU_FRAME_SIZE  (24)  /* return address, sp, and bp pushed plus fudge */
588#else
589#error "Unknown CPU!!!"
590#endif
591
592/*
593 *  Amount of extra stack (above minimum stack size) required by
594 *  MPCI receive server thread.  Remember that in a multiprocessor
595 *  system this thread must exist and be able to process all directives.
596 */
597
598#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
599
600/*
601 *  This defines the number of entries in the ISR_Vector_table managed
602 *  by RTEMS.
603 */
604
605#define CPU_INTERRUPT_NUMBER_OF_VECTORS      64
606#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
607
608/*
609 *  Should be large enough to run all RTEMS tests.  This insures
610 *  that a "reasonable" small application should not have any problems.
611 */
612
613#define CPU_STACK_MINIMUM_SIZE          (16 * 1024)
614
615/*
616 *  CPU's worst alignment requirement for data types on a byte boundary.  This
617 *  alignment does not take into account the requirements for the stack.
618 */
619
620#define CPU_ALIGNMENT              8
621
622/*
623 *  This number corresponds to the byte alignment requirement for the
624 *  heap handler.  This alignment requirement may be stricter than that
625 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
626 *  common for the heap to follow the same alignment requirement as
627 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
628 *  then this should be set to CPU_ALIGNMENT.
629 *
630 *  NOTE:  This does not have to be a power of 2.  It does have to
631 *         be greater or equal to than CPU_ALIGNMENT.
632 */
633
634#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
635
636/*
637 *  This number corresponds to the byte alignment requirement for memory
638 *  buffers allocated by the partition manager.  This alignment requirement
639 *  may be stricter than that for the data types alignment specified by
640 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
641 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
642 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
643 *
644 *  NOTE:  This does not have to be a power of 2.  It does have to
645 *         be greater or equal to than CPU_ALIGNMENT.
646 */
647
648#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
649
650/*
651 *  This number corresponds to the byte alignment requirement for the
652 *  stack.  This alignment requirement may be stricter than that for the
653 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
654 *  is strict enough for the stack, then this should be set to 0.
655 *
656 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
657 */
658
659#define CPU_STACK_ALIGNMENT        64
660
661/* ISR handler macros */
662
663/*
664 *  Disable all interrupts for an RTEMS critical section.  The previous
665 *  level is returned in _level.
666 */
667
668extern unsigned32 _CPU_ISR_Disable_support(void);
669
670#define _CPU_ISR_Disable( _level ) \
671    do { \
672      (_level) = _CPU_ISR_Disable_support(); \
673    } while ( 0 )
674
675/*
676 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
677 *  This indicates the end of an RTEMS critical section.  The parameter
678 *  _level is not modified.
679 */
680
681void _CPU_ISR_Enable(unsigned32 level);
682
683/*
684 *  This temporarily restores the interrupt to _level before immediately
685 *  disabling them again.  This is used to divide long RTEMS critical
686 *  sections into two or more parts.  The parameter _level is not
687 * modified.
688 */
689
690#define _CPU_ISR_Flash( _level ) \
691  do { \
692      register unsigned32 _ignored = 0; \
693      _CPU_ISR_Enable( (_level) ); \
694      _CPU_ISR_Disable( _ignored ); \
695  } while ( 0 )
696
697/*
698 *  Map interrupt level in task mode onto the hardware that the CPU
699 *  actually provides.  Currently, interrupt levels which do not
700 *  map onto the CPU in a generic fashion are undefined.  Someday,
701 *  it would be nice if these were "mapped" by the application
702 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
703 *  8 - 255 would be available for bsp/application specific meaning.
704 *  This could be used to manage a programmable interrupt controller
705 *  via the rtems_task_mode directive.
706 */
707
708#define _CPU_ISR_Set_level( new_level ) \
709  { \
710    if ( new_level == 0 ) _CPU_ISR_Enable( 0 ); \
711    else                  _CPU_ISR_Enable( 1 ); \
712  }
713
714unsigned32 _CPU_ISR_Get_level( void );
715
716/* end of ISR handler macros */
717
718/* Context handler macros */
719
720/*
721 *  This routine is responsible for somehow restarting the currently
722 *  executing task.  If you are lucky, then all that is necessary
723 *  is restoring the context.  Otherwise, there will need to be
724 *  a special assembly routine which does something special in this
725 *  case.  Context_Restore should work most of the time.  It will
726 *  not work if restarting self conflicts with the stack frame
727 *  assumptions of restoring a context.
728 */
729
730#define _CPU_Context_Restart_self( _the_context ) \
731   _CPU_Context_restore( (_the_context) );
732
733/*
734 *  The purpose of this macro is to allow the initial pointer into
735 *  a floating point context area (used to save the floating point
736 *  context) to be at an arbitrary place in the floating point
737 *  context area.
738 *
739 *  This is necessary because some FP units are designed to have
740 *  their context saved as a stack which grows into lower addresses.
741 *  Other FP units can be saved by simply moving registers into offsets
742 *  from the base of the context area.  Finally some FP units provide
743 *  a "dump context" instruction which could fill in from high to low
744 *  or low to high based on the whim of the CPU designers.
745 */
746
747#define _CPU_Context_Fp_start( _base, _offset ) \
748   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
749
750/*
751 *  This routine initializes the FP context area passed to it to.
752 *  There are a few standard ways in which to initialize the
753 *  floating point context.  The code included for this macro assumes
754 *  that this is a CPU in which a "initial" FP context was saved into
755 *  _CPU_Null_fp_context and it simply copies it to the destination
756 *  context passed to it.
757 *
758 *  Other models include (1) not doing anything, and (2) putting
759 *  a "null FP status word" in the correct place in the FP context.
760 */
761
762#define _CPU_Context_Initialize_fp( _destination ) \
763  { \
764   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
765  }
766
767#define _CPU_Context_save_fp( _fp_context ) \
768    _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context))
769
770#define _CPU_Context_restore_fp( _fp_context ) \
771    _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context))
772
773extern void _CPU_Context_Initialize(
774  Context_Control  *_the_context,
775  unsigned32       *_stack_base,
776  unsigned32        _size,
777  unsigned32        _new_level,
778  void             *_entry_point,
779  boolean           _is_fp
780);
781
782/* end of Context handler macros */
783
784/* Fatal Error manager macros */
785
786/*
787 *  This routine copies _error into a known place -- typically a stack
788 *  location or a register, optionally disables interrupts, and
789 *  halts/stops the CPU.
790 */
791
792#define _CPU_Fatal_halt( _error ) \
793    _CPU_Fatal_error( _error )
794
795/* end of Fatal Error manager macros */
796
797/* Bitfield handler macros */
798
799/*
800 *  This routine sets _output to the bit number of the first bit
801 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
802 *  This type may be either 16 or 32 bits wide although only the 16
803 *  least significant bits will be used.
804 *
805 *  There are a number of variables in using a "find first bit" type
806 *  instruction.
807 *
808 *    (1) What happens when run on a value of zero?
809 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
810 *    (3) The numbering may be zero or one based.
811 *    (4) The "find first bit" instruction may search from MSB or LSB.
812 *
813 *  RTEMS guarantees that (1) will never happen so it is not a concern.
814 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
815 *  _CPU_Priority_bits_index().  These three form a set of routines
816 *  which must logically operate together.  Bits in the _value are
817 *  set and cleared based on masks built by _CPU_Priority_mask().
818 *  The basic major and minor values calculated by _Priority_Major()
819 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
820 *  to properly range between the values returned by the "find first bit"
821 *  instruction.  This makes it possible for _Priority_Get_highest() to
822 *  calculate the major and directly index into the minor table.
823 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
824 *  is the first bit found.
825 *
826 *  This entire "find first bit" and mapping process depends heavily
827 *  on the manner in which a priority is broken into a major and minor
828 *  components with the major being the 4 MSB of a priority and minor
829 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
830 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
831 *  to the lowest priority.
832 *
833 *  If your CPU does not have a "find first bit" instruction, then
834 *  there are ways to make do without it.  Here are a handful of ways
835 *  to implement this in software:
836 *
837 *    - a series of 16 bit test instructions
838 *    - a "binary search using if's"
839 *    - _number = 0
840 *      if _value > 0x00ff
841 *        _value >>=8
842 *        _number = 8;
843 *
844 *      if _value > 0x0000f
845 *        _value >=8
846 *        _number += 4
847 *
848 *      _number += bit_set_table[ _value ]
849 *
850 *    where bit_set_table[ 16 ] has values which indicate the first
851 *      bit set
852 */
853
854/*
855 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
856 *  dependencies on either a native bitscan instruction or an ffs() in the
857 *  C library.
858 */
859 
860#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
861#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
862 
863/* end of Bitfield handler macros */
864 
865/* Priority handler handler macros */
866 
867/*
868 *  The UNIX port uses the generic C algorithm for bitfield scan to avoid
869 *  dependencies on either a native bitscan instruction or an ffs() in the
870 *  C library.
871 */
872 
873/* end of Priority handler macros */
874
875/* functions */
876
877/*
878 *  _CPU_Initialize
879 *
880 *  This routine performs CPU dependent initialization.
881 */
882
883void _CPU_Initialize(
884  rtems_cpu_table  *cpu_table,
885  void      (*thread_dispatch)
886);
887
888/*
889 *  _CPU_ISR_install_raw_handler
890 *
891 *  This routine installs a "raw" interrupt handler directly into the
892 *  processor's vector table.
893 */
894 
895void _CPU_ISR_install_raw_handler(
896  unsigned32  vector,
897  proc_ptr    new_handler,
898  proc_ptr   *old_handler
899);
900
901/*
902 *  _CPU_ISR_install_vector
903 *
904 *  This routine installs an interrupt vector.
905 */
906
907void _CPU_ISR_install_vector(
908  unsigned32  vector,
909  proc_ptr    new_handler,
910  proc_ptr   *old_handler
911);
912
913/*
914 *  _CPU_Install_interrupt_stack
915 *
916 *  This routine installs the hardware interrupt stack pointer.
917 *
918 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
919 *         is TRUE.
920 */
921
922void _CPU_Install_interrupt_stack( void );
923
924/*
925 *  _CPU_Thread_Idle_body
926 *
927 *  This routine is the CPU dependent IDLE thread body.
928 *
929 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
930 *         is TRUE.
931 */
932
933void _CPU_Thread_Idle_body( void );
934
935/*
936 *  _CPU_Context_switch
937 *
938 *  This routine switches from the run context to the heir context.
939 */
940
941void _CPU_Context_switch(
942  Context_Control  *run,
943  Context_Control  *heir
944);
945
946/*
947 *  _CPU_Context_restore
948 *
949 *  This routine is generally used only to restart self in an
950 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
951 *
952 *  NOTE: May be unnecessary to reload some registers.
953 */
954
955void _CPU_Context_restore(
956  Context_Control *new_context
957);
958
959/*
960 *  _CPU_Save_float_context
961 *
962 *  This routine saves the floating point context passed to it.
963 */
964
965void _CPU_Save_float_context(
966  Context_Control_fp *fp_context_ptr
967);
968
969/*
970 *  _CPU_Restore_float_context
971 *
972 *  This routine restores the floating point context passed to it.
973 */
974
975void _CPU_Restore_float_context(
976  Context_Control_fp *fp_context_ptr
977);
978
979
980void _CPU_ISR_Set_signal_level(
981  unsigned32 level
982);
983
984void _CPU_Fatal_error(
985  unsigned32 _error
986);
987
988/*  The following routine swaps the endian format of an unsigned int.
989 *  It must be static because it is referenced indirectly.
990 *
991 *  This version will work on any processor, but if there is a better
992 *  way for your CPU PLEASE use it.  The most common way to do this is to:
993 *
994 *     swap least significant two bytes with 16-bit rotate
995 *     swap upper and lower 16-bits
996 *     swap most significant two bytes with 16-bit rotate
997 *
998 *  Some CPUs have special instructions which swap a 32-bit quantity in
999 *  a single instruction (e.g. i486).  It is probably best to avoid
1000 *  an "endian swapping control bit" in the CPU.  One good reason is
1001 *  that interrupts would probably have to be disabled to insure that
1002 *  an interrupt does not try to access the same "chunk" with the wrong
1003 *  endian.  Another good reason is that on some CPUs, the endian bit
1004 *  endianness for ALL fetches -- both code and data -- so the code
1005 *  will be fetched incorrectly.
1006 */
1007 
1008static inline unsigned int CPU_swap_u32(
1009  unsigned int value
1010)
1011{
1012  unsigned32 byte1, byte2, byte3, byte4, swapped;
1013 
1014  byte4 = (value >> 24) & 0xff;
1015  byte3 = (value >> 16) & 0xff;
1016  byte2 = (value >> 8)  & 0xff;
1017  byte1 =  value        & 0xff;
1018 
1019  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1020  return( swapped );
1021}
1022
1023#define CPU_swap_u16( value ) \
1024  (((value&0xff) << 8) | ((value >> 8)&0xff))
1025
1026/*
1027 *  Special Purpose Routines to hide the use of UNIX system calls.
1028 */
1029
1030
1031/*
1032 *  Pointer to a sync io  Handler
1033 */
1034
1035typedef void ( *rtems_sync_io_handler )(
1036  int fd,
1037  boolean read,
1038  boolean wrtie,
1039  boolean except
1040);
1041
1042/* returns -1 if fd to large, 0 is successful */
1043int _CPU_Set_sync_io_handler(
1044  int fd,
1045  boolean read,
1046  boolean write,
1047  boolean except,
1048  rtems_sync_io_handler handler
1049);
1050
1051/* returns -1 if fd to large, o if successful */
1052int _CPU_Clear_sync_io_handler(
1053  int fd
1054);
1055
1056int _CPU_Get_clock_vector( void );
1057
1058void _CPU_Start_clock( 
1059  int microseconds
1060);
1061
1062void _CPU_Stop_clock( void );
1063
1064#if defined(RTEMS_MULTIPROCESSING)
1065
1066void _CPU_SHM_Init( 
1067  unsigned32   maximum_nodes,
1068  boolean      is_master_node,
1069  void       **shm_address,
1070  unsigned32  *shm_length
1071);
1072
1073int _CPU_Get_pid( void );
1074 
1075int _CPU_SHM_Get_vector( void );
1076 
1077void _CPU_SHM_Send_interrupt(
1078  int pid,
1079  int vector
1080);
1081 
1082void _CPU_SHM_Lock( 
1083  int semaphore
1084);
1085
1086void _CPU_SHM_Unlock(
1087  int semaphore
1088);
1089#endif
1090
1091#ifdef __cplusplus
1092}
1093#endif
1094
1095#endif
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